From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bghUX-0003Su-Pl for qemu-devel@nongnu.org; Sun, 04 Sep 2016 20:10:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bghUS-0002Fm-Nu for qemu-devel@nongnu.org; Sun, 04 Sep 2016 20:10:25 -0400 Message-ID: <1473034203.2313.38.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Mon, 05 Sep 2016 10:10:03 +1000 In-Reply-To: <87wpirbnwn.fsf@linaro.org> References: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> <1472797976-24210-5-git-send-email-nikunj@linux.vnet.ibm.com> <1472800972.9620.8.camel@kernel.crashing.org> <87y43akb51.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <87wpirbnwn.fsf@linaro.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the cpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?ISO-8859-1?Q?Benn=E9e?= , Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, qemu-devel@nongnu.org On Sun, 2016-09-04 at 18:00 +0100, Alex Benn=C3=A9e wrote: > When is the synchronisation point? On ARM we end the basic block on > system instructions that mess with the cache. As a result the flush > is done as soon as we exit the run loop on the next instruction. Talking o this... Nikunj, I notice, all our TLB flushing is only ever done on the "current" CPU. I mean today, without MT-TCG. That looks broken already isn't it ? Looking at ARM, they do this: /* IS variants of TLB operations must affect all cores */ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0uint64_t value) { =C2=A0=C2=A0=C2=A0=C2=A0CPUState *other_cs; =C2=A0=C2=A0=C2=A0=C2=A0CPU_FOREACH(other_cs) { =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tlb_flush(other_cs, 1); =C2=A0=C2=A0=C2=A0=C2=A0} } I wonder if we should audit all tlb_flush() calls in target-ppc to do the right thing as well ? Something like the (untested, not even compiled as I have to run) patch below. Now to do things a bit better, we could split the check_tlb_flush() helpe= r (or pass an argument) to tell it whether to check/flush other CPUs or not. All the slb operations and tlbiel only need to affect the current CPU, bu= t broadcast tlbie's (and thus H_REMOVE) should have a global affect. We cou= ld add another flag to the env in addition to the tlb_need_flush, something = like tlb_need_global_flush which is set on tlbie instructions to inform check_tlb_flush what to do. diff --git a/roms/SLOF b/roms/SLOF --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit e3d05727a074619fc12d0a67f05cf2c42c875cce +Subproject commit e3d05727a074619fc12d0a67f05cf2c42c875cce-dirty diff --git a/roms/openbios b/roms/openbios index e79bca6..46ee135 160000 --- a/roms/openbios +++ b/roms/openbios @@ -1 +1 @@ -Subproject commit e79bca64838c96ec44fd7acd508879c5284233dd +Subproject commit 46ee1352c50aa891e3dce9b3e3428ae9a5703fbe-dirty diff --git a/roms/seabios b/roms/seabios --- a/roms/seabios +++ b/roms/seabios @@ -1 +1 @@ -Subproject commit e2fc41e24ee0ada60fc511d60b15a41b294538be +Subproject commit e2fc41e24ee0ada60fc511d60b15a41b294538be-dirty diff --git a/roms/vgabios b/roms/vgabios --- a/roms/vgabios +++ b/roms/vgabios @@ -1 +1 @@ -Subproject commit 19ea12c230ded95928ecaef0db47a82231c2e485 +Subproject commit 19ea12c230ded95928ecaef0db47a82231c2e485-dirty diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 0ee0e5a..f2302ec 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -959,8 +959,13 @@ static inline void do_rfi(CPUPPCState *env, target_u= long nip, target_ulong msr) { CPUState *cs =3D CPU(ppc_env_get_cpu(env)); =20 - /* MSR:POW cannot be set by any form of rfi */ - msr &=3D ~(1ULL << MSR_POW); + /* These bits cannot be set by RFI on non-BookE systems and so must + * be filtered out. 6xx and 7xxx with SW TLB management will put + * TLB related junk in there among other things. + */ + if (!(env->excp_model & POWERPC_EXCP_BOOKE)) { + msr &=3D ~(target_ulong)0xf0000; + } =20 #if defined(TARGET_PPC64) /* Switching to 32-bit ? Crop the nip */ @@ -990,7 +995,6 @@ void helper_rfi(CPUPPCState *env) do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); } =20 -#define MSR_BOOK3S_MASK #if defined(TARGET_PPC64) void helper_rfid(CPUPPCState *env) { diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index 3d279f1..f3eb21d 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -156,10 +156,15 @@ static inline int hreg_store_msr(CPUPPCState *env, = target_ulong value, #if !defined(CONFIG_USER_ONLY) static inline void check_tlb_flush(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); - if (env->tlb_need_flush) { - env->tlb_need_flush =3D 0; - tlb_flush(cs, 1); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (env->tlb_need_flush) { + env->tlb_need_flush =3D 0; + tlb_flush(cs, 1); + } } } #else diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 8118143..a76c92b 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -907,12 +907,16 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1) { - /* - * XXX: given the fact that there are too many segments to - * invalidate, and we still don't have a tlb_flush_mask(env, n, - * mask) in QEMU, we just invalidate all TLBs - */ - tlb_flush(CPU(cpu), 1); + CPUState *cs; + + CPU_FOREACH(cs) { + /* + * XXX: given the fact that there are too many segments to + * invalidate, and we still don't have a tlb_flush_mask(env, n, + * mask) in QEMU, we just invalidate all TLBs + */ + tlb_flush(cs, 1); + } } =20 void ppc_hash64_update_rmls(CPUPPCState *env) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 696bb03..1d84fc4 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2758,6 +2758,7 @@ static inline void booke206_invalidate_ea_tlb(CPUPP= CState *env, int tlbn, void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + CPUState *other_cs; =20 if (address & 0x4) { /* flush all entries */ @@ -2774,11 +2775,15 @@ void helper_booke206_tlbivax(CPUPPCState *env, ta= rget_ulong address) if (address & 0x8) { /* flush TLB1 entries */ booke206_invalidate_ea_tlb(env, 1, address); - tlb_flush(CPU(cpu), 1); + CPU_FOREACH(other_cs) { + tlb_flush(other_cs, 1); + } } else { /* flush TLB0 entries */ booke206_invalidate_ea_tlb(env, 0, address); - tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); + CPU_FOREACH(other_cs) { + tlb_flush_page(other_cs, address & MAS2_EPN_MASK); + } } } Cheers, Ben.