* [Qemu-devel] [PATCH v4 01/10] ast2400: rename the Aspeed SoC files to aspeed_soc
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 02/10] ast2400: replace ast2400 with aspeed_soc Cédric Le Goater
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
Let's prepare for new Aspeed SoCs and rename the ast2400 file to a
more generic one. There are no changes in the code apart from the
header file include.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/{ast2400.c => aspeed_soc.c} | 2 +-
hw/arm/palmetto-bmc.c | 2 +-
include/hw/arm/{ast2400.h => aspeed_soc.h} | 0
4 files changed, 3 insertions(+), 3 deletions(-)
rename hw/arm/{ast2400.c => aspeed_soc.c} (99%)
rename include/hw/arm/{ast2400.h => aspeed_soc.h} (100%)
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 12764ef2b719..7901294630b1 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -17,4 +17,4 @@ obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
-obj-$(CONFIG_ASPEED_SOC) += ast2400.o palmetto-bmc.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o palmetto-bmc.o
diff --git a/hw/arm/ast2400.c b/hw/arm/aspeed_soc.c
similarity index 99%
rename from hw/arm/ast2400.c
rename to hw/arm/aspeed_soc.c
index 136bf6464e1d..b272f4e48cfc 100644
--- a/hw/arm/ast2400.c
+++ b/hw/arm/aspeed_soc.c
@@ -15,7 +15,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "exec/address-spaces.h"
-#include "hw/arm/ast2400.h"
+#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "hw/i2c/aspeed_i2c.h"
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index 54e29a865d88..67676a8a8042 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -15,7 +15,7 @@
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/arm/arm.h"
-#include "hw/arm/ast2400.h"
+#include "hw/arm/aspeed_soc.h"
#include "hw/boards.h"
#include "qemu/log.h"
#include "sysemu/block-backend.h"
diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/aspeed_soc.h
similarity index 100%
rename from include/hw/arm/ast2400.h
rename to include/hw/arm/aspeed_soc.h
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 02/10] ast2400: replace ast2400 with aspeed_soc
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 01/10] ast2400: rename the Aspeed SoC files to aspeed_soc Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 03/10] aspeed-soc: provide a framework to add new SoCs Cédric Le Goater
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
This is a name replacement to prepare ground for other SoCs.
Let's also remove the AST2400_SMC_BASE definition from the address
space mappings, as it is not used. This controller was removed from
the Aspeed SoC AST2500, so this provides us a better common base for
the address space mapping on both SoCs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed_soc.c | 95 ++++++++++++++++++++++-----------------------
hw/arm/palmetto-bmc.c | 4 +-
include/hw/arm/aspeed_soc.h | 16 ++++----
3 files changed, 57 insertions(+), 58 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index b272f4e48cfc..1bec478fef68 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -1,5 +1,5 @@
/*
- * AST2400 SoC
+ * ASPEED SoC family
*
* Andrew Jeffery <andrew@aj.id.au>
* Jeremy Kerr <jk@ozlabs.org>
@@ -20,20 +20,19 @@
#include "qemu/log.h"
#include "hw/i2c/aspeed_i2c.h"
-#define AST2400_UART_5_BASE 0x00184000
-#define AST2400_IOMEM_SIZE 0x00200000
-#define AST2400_IOMEM_BASE 0x1E600000
-#define AST2400_SMC_BASE AST2400_IOMEM_BASE /* Legacy SMC */
-#define AST2400_FMC_BASE 0X1E620000
-#define AST2400_SPI_BASE 0X1E630000
-#define AST2400_VIC_BASE 0x1E6C0000
-#define AST2400_SDMC_BASE 0x1E6E0000
-#define AST2400_SCU_BASE 0x1E6E2000
-#define AST2400_TIMER_BASE 0x1E782000
-#define AST2400_I2C_BASE 0x1E78A000
-
-#define AST2400_FMC_FLASH_BASE 0x20000000
-#define AST2400_SPI_FLASH_BASE 0x30000000
+#define ASPEED_SOC_UART_5_BASE 0x00184000
+#define ASPEED_SOC_IOMEM_SIZE 0x00200000
+#define ASPEED_SOC_IOMEM_BASE 0x1E600000
+#define ASPEED_SOC_FMC_BASE 0x1E620000
+#define ASPEED_SOC_SPI_BASE 0x1E630000
+#define ASPEED_SOC_VIC_BASE 0x1E6C0000
+#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
+#define ASPEED_SOC_SCU_BASE 0x1E6E2000
+#define ASPEED_SOC_TIMER_BASE 0x1E782000
+#define ASPEED_SOC_I2C_BASE 0x1E78A000
+
+#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
+#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@@ -43,29 +42,29 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
* handled by a device mapping.
*/
-static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
+static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
__func__, offset, size);
return 0;
}
-static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
+static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
__func__, offset, value, size);
}
-static const MemoryRegionOps ast2400_io_ops = {
- .read = ast2400_io_read,
- .write = ast2400_io_write,
+static const MemoryRegionOps aspeed_soc_io_ops = {
+ .read = aspeed_soc_io_read,
+ .write = aspeed_soc_io_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ast2400_init(Object *obj)
+static void aspeed_soc_init(Object *obj)
{
- AST2400State *s = AST2400(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
s->cpu = cpu_arm_init("arm926");
@@ -106,17 +105,17 @@ static void ast2400_init(Object *obj)
AST2400_A0_SILICON_REV);
}
-static void ast2400_realize(DeviceState *dev, Error **errp)
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
{
int i;
- AST2400State *s = AST2400(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
Error *err = NULL, *local_err = NULL;
/* IO space */
- memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
- "ast2400.io", AST2400_IOMEM_SIZE);
- memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
- &s->iomem, -1);
+ memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
+ "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
/* VIC */
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
@@ -124,7 +123,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
@@ -136,7 +135,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
@@ -148,12 +147,12 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hds[0]) {
qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
- serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
+ serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
}
@@ -163,7 +162,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
qdev_get_gpio_in(DEVICE(&s->vic), 12));
@@ -175,8 +174,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, AST2400_FMC_BASE);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, AST2400_FMC_FLASH_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, ASPEED_SOC_FMC_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, ASPEED_SOC_FMC_FLASH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,
qdev_get_gpio_in(DEVICE(&s->vic), 19));
@@ -188,8 +187,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE);
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
@@ -197,14 +196,14 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, AST2400_SDMC_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
}
-static void ast2400_class_init(ObjectClass *oc, void *data)
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = ast2400_realize;
+ dc->realize = aspeed_soc_realize;
/*
* Reason: creates an ARM CPU, thus use after free(), see
@@ -213,17 +212,17 @@ static void ast2400_class_init(ObjectClass *oc, void *data)
dc->cannot_destroy_with_object_finalize_yet = true;
}
-static const TypeInfo ast2400_type_info = {
- .name = TYPE_AST2400,
+static const TypeInfo aspeed_soc_type_info = {
+ .name = TYPE_ASPEED_SOC,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(AST2400State),
- .instance_init = ast2400_init,
- .class_init = ast2400_class_init,
+ .instance_size = sizeof(AspeedSoCState),
+ .instance_init = aspeed_soc_init,
+ .class_init = aspeed_soc_class_init,
};
-static void ast2400_register_types(void)
+static void aspeed_soc_register_types(void)
{
- type_register_static(&ast2400_type_info);
+ type_register_static(&aspeed_soc_type_info);
}
-type_init(ast2400_register_types)
+type_init(aspeed_soc_register_types)
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index 67676a8a8042..4d11905cfb18 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -28,7 +28,7 @@ static struct arm_boot_info palmetto_bmc_binfo = {
};
typedef struct PalmettoBMCState {
- AST2400State soc;
+ AspeedSoCState soc;
MemoryRegion ram;
} PalmettoBMCState;
@@ -63,7 +63,7 @@ static void palmetto_bmc_init(MachineState *machine)
PalmettoBMCState *bmc;
bmc = g_new0(PalmettoBMCState, 1);
- object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
+ object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_ASPEED_SOC);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
&error_abort);
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e68807d475b7..bf63ae90cabe 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -1,5 +1,5 @@
/*
- * ASPEED AST2400 SoC
+ * ASPEED SoC family
*
* Andrew Jeffery <andrew@aj.id.au>
*
@@ -9,8 +9,8 @@
* the COPYING file in the top-level directory.
*/
-#ifndef AST2400_H
-#define AST2400_H
+#ifndef ASPEED_SOC_H
+#define ASPEED_SOC_H
#include "hw/arm/arm.h"
#include "hw/intc/aspeed_vic.h"
@@ -20,7 +20,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
-typedef struct AST2400State {
+typedef struct AspeedSoCState {
/*< private >*/
DeviceState parent;
@@ -34,11 +34,11 @@ typedef struct AST2400State {
AspeedSMCState smc;
AspeedSMCState spi;
AspeedSDMCState sdmc;
-} AST2400State;
+} AspeedSoCState;
-#define TYPE_AST2400 "ast2400"
-#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
+#define TYPE_ASPEED_SOC "aspeed-soc"
+#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
#define AST2400_SDRAM_BASE 0x40000000
-#endif /* AST2400_H */
+#endif /* ASPEED_SOC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 03/10] aspeed-soc: provide a framework to add new SoCs
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 01/10] ast2400: rename the Aspeed SoC files to aspeed_soc Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 02/10] ast2400: replace ast2400 with aspeed_soc Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 04/10] palmetto-bmc: rename the Aspeed board file to aspeed.c Cédric Le Goater
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
Let's define an object class for each Aspeed SoC we support. A
AspeedSoCInfo struct gathers the SoC specifications which can later be
used by an instance of the class or by a board using the SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
Changes since v3:
- use '-1' for board ID to define device-tree-only board.
hw/arm/aspeed_soc.c | 27 ++++++++++++++++++++++++---
hw/arm/palmetto-bmc.c | 12 ++++++++----
include/hw/arm/aspeed_soc.h | 17 ++++++++++++++++-
3 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 1bec478fef68..ec6ec3546908 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -37,6 +37,13 @@
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
+#define AST2400_SDRAM_BASE 0x40000000
+
+static const AspeedSoCInfo aspeed_socs[] = {
+ { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
+ { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
+};
+
/*
* IO handlers: simply catch any reads/writes to IO addresses that aren't
* handled by a device mapping.
@@ -65,8 +72,9 @@ static const MemoryRegionOps aspeed_soc_io_ops = {
static void aspeed_soc_init(Object *obj)
{
AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- s->cpu = cpu_arm_init("arm926");
+ s->cpu = cpu_arm_init(sc->info->cpu_model);
object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
@@ -84,7 +92,7 @@ static void aspeed_soc_init(Object *obj)
object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
- AST2400_A0_SILICON_REV);
+ sc->info->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
"hw-strap1", &error_abort);
object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
@@ -102,7 +110,7 @@ static void aspeed_soc_init(Object *obj)
object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
- AST2400_A0_SILICON_REV);
+ sc->info->silicon_rev);
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -202,7 +210,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+ sc->info = (AspeedSoCInfo *) data;
dc->realize = aspeed_soc_realize;
/*
@@ -222,7 +232,18 @@ static const TypeInfo aspeed_soc_type_info = {
static void aspeed_soc_register_types(void)
{
+ int i;
+
type_register_static(&aspeed_soc_type_info);
+ for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
+ TypeInfo ti = {
+ .name = aspeed_socs[i].name,
+ .parent = TYPE_ASPEED_SOC,
+ .class_init = aspeed_soc_class_init,
+ .class_data = (void *) &aspeed_socs[i],
+ };
+ type_register(&ti);
+ }
}
type_init(aspeed_soc_register_types)
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index 4d11905cfb18..43191210f3ee 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -22,8 +22,7 @@
#include "sysemu/blockdev.h"
static struct arm_boot_info palmetto_bmc_binfo = {
- .loader_start = AST2400_SDRAM_BASE,
- .board_id = 0,
+ .board_id = -1, /* device-tree-only board */
.nb_cpus = 1,
};
@@ -61,14 +60,17 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
static void palmetto_bmc_init(MachineState *machine)
{
PalmettoBMCState *bmc;
+ AspeedSoCClass *sc;
bmc = g_new0(PalmettoBMCState, 1);
- object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_ASPEED_SOC);
+ object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0");
object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
&error_abort);
+ sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
- memory_region_add_subregion(get_system_memory(), AST2400_SDRAM_BASE,
+ memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
@@ -84,6 +86,8 @@ static void palmetto_bmc_init(MachineState *machine)
palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
palmetto_bmc_binfo.ram_size = ram_size;
+ palmetto_bmc_binfo.loader_start = sc->info->sdram_base;
+
arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
}
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bf63ae90cabe..0146a2a54a0e 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -39,6 +39,21 @@ typedef struct AspeedSoCState {
#define TYPE_ASPEED_SOC "aspeed-soc"
#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
-#define AST2400_SDRAM_BASE 0x40000000
+typedef struct AspeedSoCInfo {
+ const char *name;
+ const char *cpu_model;
+ uint32_t silicon_rev;
+ hwaddr sdram_base;
+} AspeedSoCInfo;
+
+typedef struct AspeedSoCClass {
+ DeviceState parent_class;
+ AspeedSoCInfo *info;
+} AspeedSoCClass;
+
+#define ASPEED_SOC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
+#define ASPEED_SOC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
#endif /* ASPEED_SOC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 04/10] palmetto-bmc: rename the Aspeed board file to aspeed.c
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (2 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 03/10] aspeed-soc: provide a framework to add new SoCs Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 05/10] palmetto-bmc: replace palmetto_bmc with aspeed Cédric Le Goater
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
We plan to add more Aspeed boards to this file. There are no changes
in the code.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/{palmetto-bmc.c => aspeed.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename hw/arm/{palmetto-bmc.c => aspeed.c} (100%)
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 7901294630b1..4c5c4ee76c12 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -17,4 +17,4 @@ obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
-obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o palmetto-bmc.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/aspeed.c
similarity index 100%
rename from hw/arm/palmetto-bmc.c
rename to hw/arm/aspeed.c
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 05/10] palmetto-bmc: replace palmetto_bmc with aspeed
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (3 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 04/10] palmetto-bmc: rename the Aspeed board file to aspeed.c Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 06/10] palmetto-bmc: add board specific configuration Cédric Le Goater
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
This is mostly a name replacement to prepare ground for other SoCs
specificities. It also adds a TypeInfo struct for the palmetto-bmc
board with a custom initialization for the same reason.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed.c | 54 ++++++++++++++++++++++++++++++++++++------------------
1 file changed, 36 insertions(+), 18 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 43191210f3ee..3b901eaa6fb6 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -21,17 +21,17 @@
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
-static struct arm_boot_info palmetto_bmc_binfo = {
+static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
.nb_cpus = 1,
};
-typedef struct PalmettoBMCState {
+typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
-} PalmettoBMCState;
+} AspeedBoardState;
-static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
+static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Error **errp)
{
int i ;
@@ -57,12 +57,12 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
}
}
-static void palmetto_bmc_init(MachineState *machine)
+static void aspeed_board_init(MachineState *machine)
{
- PalmettoBMCState *bmc;
+ AspeedBoardState *bmc;
AspeedSoCClass *sc;
- bmc = g_new0(PalmettoBMCState, 1);
+ bmc = g_new0(AspeedBoardState, 1);
object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0");
object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
&error_abort);
@@ -79,21 +79,28 @@ static void palmetto_bmc_init(MachineState *machine)
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
- palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
- palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
+ aspeed_board_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
+ aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
+
+ aspeed_board_binfo.kernel_filename = machine->kernel_filename;
+ aspeed_board_binfo.initrd_filename = machine->initrd_filename;
+ aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
+ aspeed_board_binfo.ram_size = ram_size;
+ aspeed_board_binfo.loader_start = sc->info->sdram_base;
- palmetto_bmc_binfo.kernel_filename = machine->kernel_filename;
- palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
- palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
- palmetto_bmc_binfo.ram_size = ram_size;
- palmetto_bmc_binfo.loader_start = sc->info->sdram_base;
+ arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
+}
- arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
+static void palmetto_bmc_init(MachineState *machine)
+{
+ aspeed_board_init(machine);
}
-static void palmetto_bmc_machine_init(MachineClass *mc)
+static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
{
- mc->desc = "OpenPOWER Palmetto BMC";
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
mc->init = palmetto_bmc_init;
mc->max_cpus = 1;
mc->no_sdcard = 1;
@@ -103,4 +110,15 @@ static void palmetto_bmc_machine_init(MachineClass *mc)
mc->no_parallel = 1;
}
-DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init);
+static const TypeInfo palmetto_bmc_type = {
+ .name = MACHINE_TYPE_NAME("palmetto-bmc"),
+ .parent = TYPE_MACHINE,
+ .class_init = palmetto_bmc_class_init,
+};
+
+static void aspeed_machine_init(void)
+{
+ type_register_static(&palmetto_bmc_type);
+}
+
+type_init(aspeed_machine_init)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 06/10] palmetto-bmc: add board specific configuration
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (4 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 05/10] palmetto-bmc: replace palmetto_bmc with aspeed Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 07/10] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC Cédric Le Goater
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
aspeed_board_init() now uses a board identifier to customize some values
specific to the board.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes since v3:
- added trailing comma to enum
Changes since v2:
- removed silicon-rev and cpu-model. This is now in the SoC.
Changes since v1:
- changed aspeed_init() prototype to use a 'const AspeedBoardConfig *'
- fixed white space issues
hw/arm/aspeed.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3b901eaa6fb6..b4eb8049af97 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -31,6 +31,19 @@ typedef struct AspeedBoardState {
MemoryRegion ram;
} AspeedBoardState;
+typedef struct AspeedBoardConfig {
+ const char *soc_name;
+ uint32_t hw_strap1;
+} AspeedBoardConfig;
+
+enum {
+ PALMETTO_BMC,
+};
+
+static const AspeedBoardConfig aspeed_boards[] = {
+ [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 },
+};
+
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Error **errp)
{
@@ -57,13 +70,14 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
}
}
-static void aspeed_board_init(MachineState *machine)
+static void aspeed_board_init(MachineState *machine,
+ const AspeedBoardConfig *cfg)
{
AspeedBoardState *bmc;
AspeedSoCClass *sc;
bmc = g_new0(AspeedBoardState, 1);
- object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0");
+ object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
&error_abort);
@@ -74,7 +88,7 @@ static void aspeed_board_init(MachineState *machine)
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
&error_abort);
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
@@ -93,7 +107,7 @@ static void aspeed_board_init(MachineState *machine)
static void palmetto_bmc_init(MachineState *machine)
{
- aspeed_board_init(machine);
+ aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
}
static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 07/10] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (5 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 06/10] palmetto-bmc: add board specific configuration Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 08/10] aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers Cédric Le Goater
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
This gives some explanation behind the magic number 0x120CE416.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes since v3:
- added brackets around macro parameters
Changes since v2:
- more precise definitions of the hw-strap1 register
- moved hw-strap1 to the board level.
hw/arm/aspeed.c | 15 +++++-
include/hw/misc/aspeed_scu.h | 118 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 132 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index b4eb8049af97..c08213c04e3f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -40,8 +40,21 @@ enum {
PALMETTO_BMC,
};
+#define PALMETTO_BMC_HW_STRAP1 ( \
+ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
+ SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
+ SCU_AST2400_HW_STRAP_ACPI_DIS | \
+ SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_LPC_RESET_PIN | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
+ SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
+ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+
static const AspeedBoardConfig aspeed_boards[] = {
- [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 },
+ [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },
};
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index fdfd982288f2..4d3e770cec21 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -36,4 +36,122 @@ typedef struct AspeedSCUState {
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
+/*
+ * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
+ * were added.
+ *
+ * Original header file :
+ * arch/arm/mach-aspeed/include/mach/regs-scu.h
+ *
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * History :
+ * 1. 2012/12/29 Ryan Chen Create
+ */
+
+/* Hardware Strapping Register definition (for Aspeed AST2400 SOC)
+ *
+ * 31:29 Software defined strapping registers
+ * 28:27 DRAM size setting (for VGA driver use)
+ * 26:24 DRAM configuration setting
+ * 23 Enable 25 MHz reference clock input
+ * 22 Enable GPIOE pass-through mode
+ * 21 Enable GPIOD pass-through mode
+ * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
+ * 19 Disable ACPI function
+ * 23,18 Clock source selection
+ * 17 Enable BMC 2nd boot watchdog timer
+ * 16 SuperIO configuration address selection
+ * 15 VGA Class Code selection
+ * 14 Enable LPC dedicated reset pin function
+ * 13:12 SPI mode selection
+ * 11:10 CPU/AHB clock frequency ratio selection
+ * 9:8 H-PLL default clock frequency selection
+ * 7 Define MAC#2 interface
+ * 6 Define MAC#1 interface
+ * 5 Enable VGA BIOS ROM
+ * 4 Boot flash memory extended option
+ * 3:2 VGA memory size selection
+ * 1:0 BMC CPU boot code selection
+ */
+#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29)
+#define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29)
+
+#define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
+#define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
+#define DRAM_SIZE_64MB 0
+#define DRAM_SIZE_128MB 1
+#define DRAM_SIZE_256MB 2
+#define DRAM_SIZE_512MB 3
+
+#define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24)
+#define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
+
+#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
+#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
+#define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19)
+
+/* bit 23, 18 [1,0] */
+#define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
+ | (((x) & 0x1) << 18))
+#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
+ | (((x) >> 18) & 0x1))
+#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
+#define AST2400_CLK_25M_IN (0x1 << 23)
+#define AST2400_CLK_24M_IN 0
+#define AST2400_CLK_48M_IN 1
+#define AST2400_CLK_25M_IN_24M_USB_CKI 2
+#define AST2400_CLK_25M_IN_48M_USB_CKI 3
+
+#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
+#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
+#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
+#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
+
+#define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12)
+#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
+#define SCU_HW_STRAP_SPI_DIS 0
+#define SCU_HW_STRAP_SPI_MASTER 1
+#define SCU_HW_STRAP_SPI_M_S_EN 2
+#define SCU_HW_STRAP_SPI_PASS_THROUGH 3
+
+#define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10)
+#define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3)
+#define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
+#define AST2400_CPU_AHB_RATIO_1_1 0
+#define AST2400_CPU_AHB_RATIO_2_1 1
+#define AST2400_CPU_AHB_RATIO_4_1 2
+#define AST2400_CPU_AHB_RATIO_3_1 3
+
+#define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3)
+#define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
+#define AST2400_CPU_384MHZ 0
+#define AST2400_CPU_360MHZ 1
+#define AST2400_CPU_336MHZ 2
+#define AST2400_CPU_408MHZ 3
+
+#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
+#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
+#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
+#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
+
+#define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3)
+#define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
+#define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2)
+#define VGA_8M_DRAM 0
+#define VGA_16M_DRAM 1
+#define VGA_32M_DRAM 2
+#define VGA_64M_DRAM 3
+
+#define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x)
+#define AST2400_NOR_BOOT 0
+#define AST2400_NAND_BOOT 1
+#define AST2400_SPI_BOOT 2
+#define AST2400_DIS_BOOT 3
+
#endif /* ASPEED_SCU_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 08/10] aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (6 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 07/10] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 09/10] arm: add support for an ast2500 evaluation board Cédric Le Goater
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
Based on previous work done by Andrew Jeffery <andrew@aj.id.au>.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes since v3:
- added brackets around macro parameters
- fixed trailing comma in enum
Changes since v2:
- more precise definitions of the hw-strap1 register
hw/arm/aspeed_soc.c | 2 ++
hw/misc/aspeed_scu.c | 45 +++++++++++++++++++++++++-
hw/misc/aspeed_sdmc.c | 1 +
include/hw/misc/aspeed_scu.h | 75 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index ec6ec3546908..2408dfe70c51 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -38,10 +38,12 @@ static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
#define AST2400_SDRAM_BASE 0x40000000
+#define AST2500_SDRAM_BASE 0x80000000
static const AspeedSoCInfo aspeed_socs[] = {
{ "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
{ "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
+ { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE },
};
/*
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index c7e2c8263f55..b1f3e6f6b87a 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -120,6 +120,41 @@ static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
[BMC_DEV_ID] = 0x00002402U
};
+/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
+/* AST2500 revision A1 */
+
+static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
+ [SYS_RST_CTRL] = 0xFFCFFEDCU,
+ [CLK_SEL] = 0xF3F40000U,
+ [CLK_STOP_CTRL] = 0x19FC3E8BU,
+ [D2PLL_PARAM] = 0x00026108U,
+ [MPLL_PARAM] = 0x00030291U,
+ [HPLL_PARAM] = 0x93000400U,
+ [MISC_CTRL1] = 0x00000010U,
+ [PCI_CTRL1] = 0x20001A03U,
+ [PCI_CTRL2] = 0x20001A03U,
+ [PCI_CTRL3] = 0x04000030U,
+ [SYS_RST_STATUS] = 0x00000001U,
+ [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
+ [MISC_CTRL2] = 0x00000023U,
+ [RNG_CTRL] = 0x0000000EU,
+ [PINMUX_CTRL2] = 0x0000F000U,
+ [PINMUX_CTRL3] = 0x03000000U,
+ [PINMUX_CTRL4] = 0x00000000U,
+ [PINMUX_CTRL5] = 0x0000A000U,
+ [WDT_RST_CTRL] = 0x023FFFF3U,
+ [PINMUX_CTRL8] = 0xFFFF0000U,
+ [PINMUX_CTRL9] = 0x000FFFFFU,
+ [FREE_CNTR4] = 0x000000FFU,
+ [FREE_CNTR4_EXT] = 0x000000FFU,
+ [CPU2_BASE_SEG1] = 0x80000000U,
+ [CPU2_BASE_SEG4] = 0x1E600000U,
+ [CPU2_BASE_SEG5] = 0xC0000000U,
+ [UART_HPLL_CLK] = 0x00001903U,
+ [PCIE_CTRL] = 0x0000007BU,
+ [BMC_DEV_ID] = 0x00002402U
+};
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -198,6 +233,10 @@ static void aspeed_scu_reset(DeviceState *dev)
case AST2400_A0_SILICON_REV:
reset = ast2400_a0_resets;
break;
+ case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
+ reset = ast2500_a1_resets;
+ break;
default:
g_assert_not_reached();
}
@@ -208,7 +247,11 @@ static void aspeed_scu_reset(DeviceState *dev)
s->regs[HW_STRAP2] = s->hw_strap2;
}
-static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };
+static uint32_t aspeed_silicon_revs[] = {
+ AST2400_A0_SILICON_REV,
+ AST2500_A0_SILICON_REV,
+ AST2500_A1_SILICON_REV,
+};
bool is_supported_silicon_rev(uint32_t silicon_rev)
{
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 6cc0301a6331..621d166890fa 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -196,6 +196,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
break;
case AST2500_A0_SILICON_REV:
+ case AST2500_A1_SILICON_REV:
s->regs[R_CONF] |=
ASPEED_SDMC_HW_VERSION(1) |
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 4d3e770cec21..14ffc43de809 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -33,6 +33,7 @@ typedef struct AspeedSCUState {
#define AST2400_A0_SILICON_REV 0x02000303U
#define AST2500_A0_SILICON_REV 0x04000303U
+#define AST2500_A1_SILICON_REV 0x04010303U
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
@@ -154,4 +155,78 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#define AST2400_SPI_BOOT 2
#define AST2400_DIS_BOOT 3
+/*
+ * Hardware strapping register definition (for Aspeed AST2500 SoC and
+ * higher)
+ *
+ * 31 Enable SPI Flash Strap Auto Fetch Mode
+ * 30 Enable GPIO Strap Mode
+ * 29 Select UART Debug Port
+ * 28 Reserved (1)
+ * 27 Enable fast reset mode for ARM ICE debugger
+ * 26 Enable eSPI flash mode
+ * 25 Enable eSPI mode
+ * 24 Select DDR4 SDRAM
+ * 23 Select 25 MHz reference clock input mode
+ * 22 Enable GPIOE pass-through mode
+ * 21 Enable GPIOD pass-through mode
+ * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
+ * 19 Enable ACPI function
+ * 18 Select USBCKI input frequency
+ * 17 Enable BMC 2nd boot watchdog timer
+ * 16 SuperIO configuration address selection
+ * 15 VGA Class Code selection
+ * 14 Select dedicated LPC reset input
+ * 13:12 SPI mode selection
+ * 11:9 AXI/AHB clock frequency ratio selection
+ * 8 Reserved (0)
+ * 7 Define MAC#2 interface
+ * 6 Define MAC#1 interface
+ * 5 Enable dedicated VGA BIOS ROM
+ * 4 Reserved (0)
+ * 3:2 VGA memory size selection
+ * 1 Reserved (1)
+ * 0 Disable CPU boot
+ */
+#define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31)
+#define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
+#define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29)
+#define UART_DEBUG_UART1 0
+#define UART_DEBUG_UART5 1
+#define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
+
+#define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
+#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
+#define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
+#define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
+
+#define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)
+#define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)
+#define USBCKI_FREQ_24MHZ 0
+#define USBCKI_FREQ_28MHZ 1
+
+#define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9)
+#define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7)
+#define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9)
+#define AXI_AHB_RATIO_UNDEFINED 0
+#define AXI_AHB_RATIO_2_1 1
+#define AXI_AHB_RATIO_3_1 2
+#define AXI_AHB_RATIO_4_1 3
+#define AXI_AHB_RATIO_5_1 4
+#define AXI_AHB_RATIO_6_1 5
+#define AXI_AHB_RATIO_7_1 6
+#define AXI_AHB_RATIO_8_1 7
+
+#define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1)
+#define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0)
+
+#define AST2500_HW_STRAP1_DEFAULTS ( \
+ SCU_AST2500_HW_STRAP_RESERVED28 | \
+ SCU_HW_STRAP_2ND_BOOT_WDT | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_LPC_RESET_PIN | \
+ SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
+ SCU_AST2500_HW_STRAP_RESERVED1)
+
#endif /* ASPEED_SCU_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 09/10] arm: add support for an ast2500 evaluation board
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (7 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 08/10] aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 10/10] palmetto-bmc: remove extra no_sdcard assignement Cédric Le Goater
2016-09-05 16:21 ` [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
The ast2500 eval board has a hardware strapping register value of
0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1
below.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes since v3:
- fixed trailing comma.
hw/arm/aspeed.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c08213c04e3f..2af9fe934441 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -38,6 +38,7 @@ typedef struct AspeedBoardConfig {
enum {
PALMETTO_BMC,
+ AST2500_EVB,
};
#define PALMETTO_BMC_HW_STRAP1 ( \
@@ -53,8 +54,19 @@ enum {
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+#define AST2500_EVB_HW_STRAP1 (( \
+ AST2500_HW_STRAP1_DEFAULTS | \
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
+ SCU_HW_STRAP_MAC1_RGMII | \
+ SCU_HW_STRAP_MAC0_RGMII) & \
+ ~SCU_HW_STRAP_2ND_BOOT_WDT)
+
static const AspeedBoardConfig aspeed_boards[] = {
[PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },
+ [AST2500_EVB] = { "ast2500-a1", AST2500_EVB_HW_STRAP1 },
};
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
@@ -143,9 +155,34 @@ static const TypeInfo palmetto_bmc_type = {
.class_init = palmetto_bmc_class_init,
};
+static void ast2500_evb_init(MachineState *machine)
+{
+ aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
+}
+
+static void ast2500_evb_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST2500 EVB (ARM1176)";
+ mc->init = ast2500_evb_init;
+ mc->max_cpus = 1;
+ mc->no_sdcard = 1;
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->no_parallel = 1;
+}
+
+static const TypeInfo ast2500_evb_type = {
+ .name = MACHINE_TYPE_NAME("ast2500-evb"),
+ .parent = TYPE_MACHINE,
+ .class_init = ast2500_evb_class_init,
+};
+
static void aspeed_machine_init(void)
{
type_register_static(&palmetto_bmc_type);
+ type_register_static(&ast2500_evb_type);
}
type_init(aspeed_machine_init)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Qemu-devel] [PATCH v4 10/10] palmetto-bmc: remove extra no_sdcard assignement
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (8 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 09/10] arm: add support for an ast2500 evaluation board Cédric Le Goater
@ 2016-09-05 6:00 ` Cédric Le Goater
2016-09-05 16:21 ` [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2016-09-05 6:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 2af9fe934441..9013d35a674c 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -145,7 +145,6 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
mc->no_sdcard = 1;
mc->no_floppy = 1;
mc->no_cdrom = 1;
- mc->no_sdcard = 1;
mc->no_parallel = 1;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support
2016-09-05 5:59 [Qemu-devel] [PATCH v4 00/10] arm: add ast2500 support Cédric Le Goater
` (9 preceding siblings ...)
2016-09-05 6:00 ` [Qemu-devel] [PATCH v4 10/10] palmetto-bmc: remove extra no_sdcard assignement Cédric Le Goater
@ 2016-09-05 16:21 ` Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Peter Maydell @ 2016-09-05 16:21 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: QEMU Developers, qemu-arm
On 5 September 2016 at 06:59, Cédric Le Goater <clg@kaod.org> wrote:
> The AST2500 SoC being very close to the AST2400 SoC, the goal of the
> changes below is to modify the existing platform palmetto-bmc and the
> AST2400 SoC to take into account the small differences and avoid code
> duplication. This is mostly inspired by the realview and the rpi2
> platforms.
>
> First patches rework the 'palmetto-bmc' platform and the 'ast2400' SoC
> models to provide room to other platforms and SoCs which have a common
> design.
>
> The last patches add support for the new AST2500 SoC in the required
> controller (SDMC and SCU) and define a new platform for an Aspeed
> evaluation board.
>
Thanks, applied to target-arm.next.
-- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread