From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk8B-0000VP-0m for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhk8A-0002mx-3M for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:38 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34233) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk89-0002mt-Us for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:38 -0400 Received: by mail-yw0-x242.google.com with SMTP id j1so1172292ywb.1 for ; Wed, 07 Sep 2016 14:11:37 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 7 Sep 2016 14:10:42 -0700 Message-Id: <1473282648-23487-13-git-send-email-rth@twiddle.net> In-Reply-To: <1473282648-23487-1-git-send-email-rth@twiddle.net> References: <1473282648-23487-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 12/18] tcg/sparc: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Pranith Kumar From: Pranith Kumar Signed-off-by: Pranith Kumar Message-Id: <20160714202026.9727-10-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.inc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 10e4126..bca25e2 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = { #define STWA (INSN_OP(3) | INSN_OP3(0x14)) #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) +#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -835,6 +837,12 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) tcg_out_nop(s); } +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ + tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); +} + #ifdef CONFIG_SOFTMMU static tcg_insn_unit *qemu_ld_trampoline[16]; static tcg_insn_unit *qemu_st_trampoline[16]; @@ -1465,6 +1473,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); break; + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1566,6 +1578,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_st_i32, { "sZ", "A" } }, { INDEX_op_qemu_st_i64, { "SZ", "A" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.7.4