From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Pranith Kumar <bobby.prani@gmail.com>
Subject: [Qemu-devel] [PULL 16/18] target-aarch64: Generate fences for aarch64
Date: Wed, 7 Sep 2016 14:10:46 -0700 [thread overview]
Message-ID: <1473282648-23487-17-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1473282648-23487-1-git-send-email-rth@twiddle.net>
From: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160714202026.9727-14-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f5e29d2..09877bc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1305,7 +1305,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
return;
case 4: /* DSB */
case 5: /* DMB */
- /* We don't emulate caches so barriers are no-ops */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* ISB */
/* We need to break the TB after this insn to execute
@@ -1934,7 +1934,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (!is_store) {
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
} else {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
}
} else {
@@ -1943,11 +1949,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
/* Generate ISS for non-exclusive accesses including LASR. */
if (is_store) {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, is_lasr);
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
true, rt, iss_sf, is_lasr);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
}
}
}
--
2.7.4
next prev parent reply other threads:[~2016-09-07 21:11 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-07 21:10 [Qemu-devel] [PULL 00/18] tcg queued patches Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 01/18] tcg: Support arbitrary size + alignment Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 02/18] tcg: Merge GETPC and GETRA Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 03/18] cpu-exec: Check -dfilter for -d cpu Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 04/18] Introduce TCGOpcode for memory barrier Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 05/18] tcg/i386: Add support for fence Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 06/18] tcg/aarch64: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 07/18] tcg/arm: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 08/18] tcg/ia64: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 09/18] tcg/mips: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 10/18] tcg/ppc: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 11/18] tcg/s390: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 12/18] tcg/sparc: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 13/18] tcg/tci: " Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 14/18] target-arm: Generate fences in ARMv7 frontend Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 15/18] target-alpha: Generate fence op Richard Henderson
2016-09-07 21:10 ` Richard Henderson [this message]
2016-09-07 21:10 ` [Qemu-devel] [PULL 17/18] target-i386: Generate fences for x86 Richard Henderson
2016-09-07 21:10 ` [Qemu-devel] [PULL 18/18] tcg: Optimize fence instructions Richard Henderson
2016-09-08 17:15 ` [Qemu-devel] [PULL v2 00/18] tcg queued patches Richard Henderson
2016-09-08 20:38 ` Richard Henderson
2016-09-08 23:49 ` Pranith Kumar
2016-09-09 0:06 ` Pranith Kumar
2016-09-09 6:51 ` Richard Henderson
2016-09-12 17:23 ` Richard Henderson
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