From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk82-0000MO-0t for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhk80-0002jO-Ui for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:29 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:36075) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk80-0002jG-R6 for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:28 -0400 Received: by mail-yw0-x242.google.com with SMTP id q4so1171733ywq.3 for ; Wed, 07 Sep 2016 14:11:28 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 7 Sep 2016 14:10:36 -0700 Message-Id: <1473282648-23487-7-git-send-email-rth@twiddle.net> In-Reply-To: <1473282648-23487-1-git-send-email-rth@twiddle.net> References: <1473282648-23487-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 06/18] tcg/aarch64: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Pranith Kumar , Claudio Fontana From: Pranith Kumar Cc: Claudio Fontana Signed-off-by: Pranith Kumar Message-Id: <20160714202026.9727-4-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 2f5629e..6caa9a4 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -372,6 +372,11 @@ typedef enum { I3510_EOR = 0x4a000000, I3510_EON = 0x4a200000, I3510_ANDS = 0x6a000000, + + /* System instructions. */ + DMB_ISH = 0xd50338bf, + DMB_LD = 0x00000100, + DMB_ST = 0x00000200, } AArch64Insn; static inline uint32_t tcg_in32(TCGContext *s) @@ -981,6 +986,20 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, tcg_out_mov(s, ext, orig_rl, rl); } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + uint32_t dmb_type = DMB_ISH; + a0 &= TCG_MO_ALL; + if (a0 == TCG_MO_LD_LD) { + dmb_type |= DMB_LD; + } else if (a0 == TCG_MO_ST_ST) { + dmb_type |= DMB_ST; + } else { + dmb_type |= DMB_LD | DMB_ST; + } + tcg_out32(s, dmb_type); +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1647,6 +1666,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); break; + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1771,6 +1794,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_muluh_i64, { "r", "r", "r" } }, { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.7.4