From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk82-0000NX-U9 for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhk81-0002jx-TS for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:30 -0400 Received: from mail-yw0-x244.google.com ([2607:f8b0:4002:c05::244]:34959) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk81-0002jr-PX for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:29 -0400 Received: by mail-yw0-x244.google.com with SMTP id t137so1175989ywg.2 for ; Wed, 07 Sep 2016 14:11:29 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 7 Sep 2016 14:10:37 -0700 Message-Id: <1473282648-23487-8-git-send-email-rth@twiddle.net> In-Reply-To: <1473282648-23487-1-git-send-email-rth@twiddle.net> References: <1473282648-23487-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 07/18] tcg/arm: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Pranith Kumar , Andrzej Zaborowski From: Pranith Kumar Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Pranith Kumar Message-Id: <20160714202026.9727-5-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 58ffc0d..f3ff6f2 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -313,6 +313,10 @@ typedef enum { INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + } ARMInsn; #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) @@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) } } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1928,6 +1941,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; + case INDEX_op_mb: + tcg_out_mb(s, args[0]); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -2002,6 +2019,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.7.4