From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk85-0000OI-Em for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhk83-0002kj-5H for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:32 -0400 Received: from mail-yb0-x244.google.com ([2607:f8b0:4002:c09::244]:36383) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhk83-0002kW-12 for qemu-devel@nongnu.org; Wed, 07 Sep 2016 17:11:31 -0400 Received: by mail-yb0-x244.google.com with SMTP id u125so531819ybg.3 for ; Wed, 07 Sep 2016 14:11:31 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 7 Sep 2016 14:10:38 -0700 Message-Id: <1473282648-23487-9-git-send-email-rth@twiddle.net> In-Reply-To: <1473282648-23487-1-git-send-email-rth@twiddle.net> References: <1473282648-23487-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 08/18] tcg/ia64: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Pranith Kumar , Aurelien Jarno From: Pranith Kumar Cc: Aurelien Jarno Signed-off-by: Pranith Kumar Message-Id: <20160714202026.9727-6-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.inc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c index 7642390..b04d716 100644 --- a/tcg/ia64/tcg-target.inc.c +++ b/tcg/ia64/tcg-target.inc.c @@ -247,6 +247,7 @@ enum { OPC_LD4_M3 = 0x0a080000000ull, OPC_LD8_M1 = 0x080c0000000ull, OPC_LD8_M3 = 0x0a0c0000000ull, + OPC_MF_M24 = 0x00110000000ull, OPC_MUX1_I3 = 0x0eca0000000ull, OPC_NOP_B9 = 0x04008000000ull, OPC_NOP_F16 = 0x00008000000ull, @@ -2231,6 +2232,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args); break; + case INDEX_op_mb: + tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2344,6 +2348,7 @@ static const TCGTargetOpDef ia64_op_defs[] = { { INDEX_op_qemu_st_i32, { "SZ", "r" } }, { INDEX_op_qemu_st_i64, { "SZ", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.7.4