From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjNLG-00008f-95 for qemu-devel@nongnu.org; Mon, 12 Sep 2016 05:15:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bjNLC-0001lC-1q for qemu-devel@nongnu.org; Mon, 12 Sep 2016 05:15:53 -0400 Message-ID: <1473671732.8689.243.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Mon, 12 Sep 2016 19:15:32 +1000 In-Reply-To: <87zindwlyw.fsf@linaro.org> References: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> <1472797976-24210-4-git-send-email-nikunj@linux.vnet.ibm.com> <20160907040252.GJ2780@voom.fritz.box> <87d1kgjoy9.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20160907053459.GM2780@voom.fritz.box> <87d1kgyyg4.fsf@linaro.org> <20160912011912.GC12621@voom.fritz.box> <87zindwlyw.fsf@linaro.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?ISO-8859-1?Q?Benn=E9e?= , David Gibson Cc: Nikunj A Dadhania , qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org On Mon, 2016-09-12 at 09:39 +0100, Alex Benn=C3=A9e wrote: >=C2=A0 > They are now in Richard's tcg-next queue >=20 > Message-Id: <1473282648-23487-1-git-send-email-rth@twiddle.net> > Subject: [Qemu-devel] [PULL 00/18] tcg queued patches >=20 > All the backends support the new fence op, so far only ARM, Alpha and > x86 emit the fence TCGOps as these are best added by someone who > understands the frontend well. Hrm, I should probably have a look ;-) A bit swamped this week, I'll see what I can do. Cheers, Ben. > >=20 > > >=20 > > > >=20 > > > >=20 > > > > I think this does matter, IIRC a kernel spin unlock on ppc is a > > > > barrier + plain store, no load locked or store conditional. > > > >=20 > > > > >=20 > > > > > >=20 > > > > > > Specifically a racing store which happens to store the same > > > > > > value > > > > > > which was already in memory should clobber the reservation, > > > > > > but won't > > > > > > with this implementation. > > > > > >=20 > > > > > > I had a long discussion at KVM Forum with Emilio Costa > > > > > > about this, in > > > > > > which I discovered just how hard it is to strictly > > > > > > implement > > > > > > store-conditional semantics in terms of anything else.=C2=A0=C2= =A0So, > > > > > > this is > > > > > > probably a reasonable substitute, but we should note the > > > > > > fact that > > > > > > it's not 100%. > > > > >=20 > > > > > I will update the commit log. > > > > >=20 > > > > > Regards, > > > > > Nikunj > > > > >=20 > > >=20 > > >=20 >=20 >=20 > -- > Alex Benn=C3=A9e