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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Pranith Kumar <bobby.prani@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL v3 08/18] tcg/ia64: Add support for fence
Date: Mon, 12 Sep 2016 16:39:42 -0700	[thread overview]
Message-ID: <1473723592-524-9-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1473723592-524-1-git-send-email-rth@twiddle.net>

From: Pranith Kumar <bobby.prani@gmail.com>

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160714202026.9727-6-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ia64/tcg-target.inc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index 7642390..b04d716 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg/ia64/tcg-target.inc.c
@@ -247,6 +247,7 @@ enum {
     OPC_LD4_M3                = 0x0a080000000ull,
     OPC_LD8_M1                = 0x080c0000000ull,
     OPC_LD8_M3                = 0x0a0c0000000ull,
+    OPC_MF_M24                = 0x00110000000ull,
     OPC_MUX1_I3               = 0x0eca0000000ull,
     OPC_NOP_B9                = 0x04008000000ull,
     OPC_NOP_F16               = 0x00008000000ull,
@@ -2231,6 +2232,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_qemu_st(s, args);
         break;
 
+    case INDEX_op_mb:
+        tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I);
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -2344,6 +2348,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
     { INDEX_op_qemu_st_i32, { "SZ", "r" } },
     { INDEX_op_qemu_st_i64, { "SZ", "r" } },
 
+    { INDEX_op_mb, { } },
     { -1 },
 };
 
-- 
2.7.4

  parent reply	other threads:[~2016-09-12 23:41 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-12 23:39 [Qemu-devel] [PULL v3 00/18] tcg queued patches Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 01/18] tcg: Support arbitrary size + alignment Richard Henderson
2016-09-20 10:16   ` Bharata B Rao
2016-09-20 18:57     ` Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 02/18] tcg: Merge GETPC and GETRA Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 03/18] cpu-exec: Check -dfilter for -d cpu Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 04/18] Introduce TCGOpcode for memory barrier Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 05/18] tcg/i386: Add support for fence Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 06/18] tcg/aarch64: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 07/18] tcg/arm: " Richard Henderson
2016-09-12 23:39 ` Richard Henderson [this message]
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 09/18] tcg/mips: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 10/18] tcg/ppc: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 11/18] tcg/s390: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 12/18] tcg/sparc: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 13/18] tcg/tci: " Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 14/18] target-arm: Generate fences in ARMv7 frontend Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 15/18] target-alpha: Generate fence op Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 16/18] target-aarch64: Generate fences for aarch64 Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 17/18] target-i386: Generate fences for x86 Richard Henderson
2016-09-12 23:39 ` [Qemu-devel] [PULL v3 18/18] tcg: Optimize fence instructions Richard Henderson
2016-09-13 10:39 ` [Qemu-devel] [PULL v3 00/18] tcg queued patches Peter Maydell

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