From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bk6xB-0004VV-L9 for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bk6x6-0000Cr-CY for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:05 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36230) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bk6x6-0000Ci-3r for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:00 -0400 Received: by mail-wm0-f68.google.com with SMTP id b184so1733464wma.3 for ; Wed, 14 Sep 2016 02:57:59 -0700 (PDT) Received: from donizetti.lan (94-39-176-182.adsl-ull.clienti.tiscali.it. [94.39.176.182]) by smtp.gmail.com with ESMTPSA id v73sm9876453wmf.19.2016.09.14.02.56.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Sep 2016 02:56:58 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Wed, 14 Sep 2016 11:56:51 +0200 Message-Id: <1473847013-20191-2-git-send-email-pbonzini@redhat.com> In-Reply-To: <1473847013-20191-1-git-send-email-pbonzini@redhat.com> References: <1473847013-20191-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 1/3] target-arm: introduce cpu_dynamic_tb_cpu_flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org For now, this just moves computation of the TranslationBlock flags to a separate function. Later on, dynamic flags will be distinct from static flags in that static flags need not be recomputed on every TranslationBlock lookup; hence the name of the function. Signed-off-by: Paolo Bonzini --- target-arm/cpu.h | 43 ++++++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 76d824d..ef195bd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -2319,31 +2319,30 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) +static inline uint32_t cpu_dynamic_tb_cpu_flags(CPUARMState *env) { + uint32_t flags = 0; + if (is_a64(env)) { - *pc = env->pc; - *flags = ARM_TBFLAG_AARCH64_STATE_MASK; + flags |= ARM_TBFLAG_AARCH64_STATE_MASK; } else { - *pc = env->regs[15]; - *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + flags |= (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); if (!(access_secure_reg(env))) { - *flags |= ARM_TBFLAG_NS_MASK; + flags |= ARM_TBFLAG_NS_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - *flags |= ARM_TBFLAG_VFPEN_MASK; + flags |= ARM_TBFLAG_VFPEN_MASK; } - *flags |= (extract32(env->cp15.c15_cpar, 0, 2) + flags |= (extract32(env->cp15.c15_cpar, 0, 2) << ARM_TBFLAG_XSCALE_CPAR_SHIFT); } - *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT); + flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State @@ -2352,21 +2351,35 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; + flags |= ARM_TBFLAG_SS_ACTIVE_MASK; if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags |= ARM_TBFLAG_PSTATE_SS_MASK; } } else { if (env->uncached_cpsr & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags |= ARM_TBFLAG_PSTATE_SS_MASK; } } } if (arm_cpu_data_is_big_endian(env)) { - *flags |= ARM_TBFLAG_BE_DATA_MASK; + flags |= ARM_TBFLAG_BE_DATA_MASK; } - *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + + return flags; +} + +static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + *flags = cpu_dynamic_tb_cpu_flags(env); + + if (is_a64(env)) { + *pc = env->pc; + } else { + *pc = env->regs[15]; + } *cs_base = 0; } -- 2.7.4