From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bk6xB-0004VU-Hx for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bk6xA-0000E0-MW for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:05 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:35477) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bk6xA-0000DN-GI for qemu-devel@nongnu.org; Wed, 14 Sep 2016 05:58:04 -0400 Received: by mail-wm0-f68.google.com with SMTP id c131so1731641wmh.2 for ; Wed, 14 Sep 2016 02:58:02 -0700 (PDT) Received: from donizetti.lan (94-39-176-182.adsl-ull.clienti.tiscali.it. [94.39.176.182]) by smtp.gmail.com with ESMTPSA id v73sm9876453wmf.19.2016.09.14.02.57.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Sep 2016 02:57:00 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Wed, 14 Sep 2016 11:56:53 +0200 Message-Id: <1473847013-20191-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1473847013-20191-1-git-send-email-pbonzini@redhat.com> References: <1473847013-20191-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 3/3] target-arm: cache most tbflags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Finally, this patch makes most flags static. The only remaining dynamic flags (only used in aarch32 mode) are for Thumb mode and conditional execution. These are modified more often than the others, and are cheap therefore they are looked up directly from env on every TB lookup. Signed-off-by: Paolo Bonzini --- target-arm/cpu.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5918df5..0b72740 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -2320,17 +2320,15 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -static inline uint32_t cpu_dynamic_tb_cpu_flags(CPUARMState *env) +static inline uint32_t cpu_get_tb_cpu_flags(CPUARMState *env) { uint32_t flags = 0; if (is_a64(env)) { flags |= ARM_TBFLAG_AARCH64_STATE_MASK; } else { - flags |= (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) + flags |= (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); if (!(access_secure_reg(env))) { flags |= ARM_TBFLAG_NS_MASK; @@ -2371,10 +2369,15 @@ static inline uint32_t cpu_dynamic_tb_cpu_flags(CPUARMState *env) return flags; } -static inline uint32_t cpu_get_tb_cpu_flags(CPUARMState *env) +static inline uint32_t cpu_dynamic_tb_cpu_flags(CPUARMState *env) { uint32_t flags = 0; + if (!is_a64(env)) { + flags |= (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); + } + return flags; } -- 2.7.4