From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkW3v-0002OA-Sa for qemu-devel@nongnu.org; Thu, 15 Sep 2016 08:46:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkW3r-0007sj-Md for qemu-devel@nongnu.org; Thu, 15 Sep 2016 08:46:42 -0400 Received: from 9.mo177.mail-out.ovh.net ([46.105.72.238]:44969) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkW3r-0007sE-H2 for qemu-devel@nongnu.org; Thu, 15 Sep 2016 08:46:39 -0400 Received: from player699.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 8747DFFCE56 for ; Thu, 15 Sep 2016 14:46:36 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Thu, 15 Sep 2016 14:45:54 +0200 Message-Id: <1473943560-14846-5-git-send-email-clg@kaod.org> In-Reply-To: <1473943560-14846-1-git-send-email-clg@kaod.org> References: <1473943560-14846-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 04/10] ppc/pnv: add a PIR handler to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Cedric Le Goater P9 and P8 have some differences in the CPU PIR encoding. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 1 + 2 files changed, 15 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ec7dd6ac5ea1..f4c125503249 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -238,6 +238,16 @@ static void ppc_powernv_init(MachineState *machine) g_free(chip_typename); } =20 +static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 7) | (core_id << 3); +} + +static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 8) | (core_id << 2); +} + /* Allowed core identifiers on a POWER8 Processor Chip : * * @@ -273,6 +283,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8E"; } =20 @@ -292,6 +303,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8"; } =20 @@ -311,6 +323,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 @@ -330,6 +343,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask =3D POWER9_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p9; dc->desc =3D "PowerNV Chip POWER9"; } =20 diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index cfc32586320f..2bd2294ac2a3 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -58,6 +58,7 @@ typedef struct PnvChipClass { uint64_t cores_mask; =20 void (*realize)(PnvChip *dev, Error **errp); + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; =20 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" --=20 2.7.4