From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32987) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkqkc-00058Z-Ri for qemu-devel@nongnu.org; Fri, 16 Sep 2016 06:52:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkqkX-0005Yr-4Q for qemu-devel@nongnu.org; Fri, 16 Sep 2016 06:52:09 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:55581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkqkW-0005YN-Ri for qemu-devel@nongnu.org; Fri, 16 Sep 2016 06:52:05 -0400 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8GAlqiK142762 for ; Fri, 16 Sep 2016 06:52:03 -0400 Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) by mx0a-001b2d01.pphosted.com with ESMTP id 25fr9jpxwm-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 16 Sep 2016 06:52:03 -0400 Received: from localhost by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 16 Sep 2016 20:52:01 +1000 From: Nikunj A Dadhania Date: Fri, 16 Sep 2016 16:21:46 +0530 Message-Id: <1474023111-11992-1-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v3 0/5] POWER9 TCG enablements - part4(pending) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org This series contains 4 new instructions for POWER9 ISA3.0 Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x. Patches: 01: darn: Deliver a random number 02: lxvw4x - improve implementation 03: stxv4x - improve implementation 04: lxvh8x: Load VSX Vector Halfword*8 stxvh8x: Store VSX Vector Halfword*8 05: lxvb16x: Load VSX Vector Byte*16 stxvb16x: Store VSX Vector Byte*16 Changelog: v2: * Fix lxvw4x/stxv4x translation as LE/BE were both similar one in tcg and other as helper * Rename bswap32x2 to deposit32x2 as it does not need to swap content(32bit) * stxvh8x had a bug as David suggested. v1: * More load/store cleanups in byte reverse routines * ld64/st64 converted to newer macro and updated call sites * Cleanup load with reservation and store conditional * Return invalid random for darn instruction v0: * darn - read /dev/random to get the random number * xxspltib - make is PPC64 only * Consolidate load/store operations and use macros to generate qemu_st/ld * Simplify load/store vsx endian manipulation Nikunj A Dadhania (4): target-ppc: improve lxvw4x implementation target-ppc: improve stxvw4x implementation target-ppc: add lxvh8x and stxvh8x target-ppc: add lxvb16x and stxvb16x Ravi Bangoria (1): target-ppc: implement darn instruction target-ppc/helper.h | 4 + target-ppc/int_helper.c | 16 ++++ target-ppc/mem_helper.c | 11 +++ target-ppc/translate.c | 18 +++++ target-ppc/translate/vsx-impl.inc.c | 146 ++++++++++++++++++++++++++++++------ target-ppc/translate/vsx-ops.inc.c | 4 + 6 files changed, 175 insertions(+), 24 deletions(-) -- 2.7.4