From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmWiF-0005K6-3d for qemu-devel@nongnu.org; Tue, 20 Sep 2016 21:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bmWiA-0006NI-4V for qemu-devel@nongnu.org; Tue, 20 Sep 2016 21:52:38 -0400 Message-ID: <1474422722.2857.107.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Wed, 21 Sep 2016 11:52:02 +1000 In-Reply-To: <20160921012903.GO20488@umbus> References: <1473943560-14846-1-git-send-email-clg@kaod.org> <1473943560-14846-5-git-send-email-clg@kaod.org> <20160921012903.GO20488@umbus> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 04/10] ppc/pnv: add a PIR handler to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , =?ISO-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Wed, 2016-09-21 at 11:29 +1000, David Gibson wrote: > On Thu, Sep 15, 2016 at 02:45:54PM +0200, C=C3=A9dric Le Goater wrote: > >=20 > > P9 and P8 have some differences in the CPU PIR encoding. >=20 > The thread id isn't in the PIR at all? Yes it is. Though on P9 there could be different encodings depending on some kind of "mode" I can't quite yet get into details about. Cheers, Ben. > >=20 > >=20 > > Signed-off-by: C=C3=A9dric Le Goater > > --- > > =C2=A0hw/ppc/pnv.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0| 14 ++++++++++++++ > > =C2=A0include/hw/ppc/pnv.h |=C2=A0=C2=A01 + > > =C2=A02 files changed, 15 insertions(+) > >=20 > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > > index ec7dd6ac5ea1..f4c125503249 100644 > > --- a/hw/ppc/pnv.c > > +++ b/hw/ppc/pnv.c > > @@ -238,6 +238,16 @@ static void ppc_powernv_init(MachineState > > *machine) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0g_free(chip_typename); > > =C2=A0} > > =C2=A0 > > +static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t > > core_id) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0return (chip->chip_id << 7) | (core_id << 3)= ; > > +} > > + > > +static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t > > core_id) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0return (chip->chip_id << 8) | (core_id << 2)= ; > > +} > > + > > =C2=A0/* Allowed core identifiers on a POWER8 Processor Chip : > > =C2=A0 * > > =C2=A0 * > > @@ -273,6 +283,7 @@ static void > > pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_type =3D PNV_CHIP_POWER8E; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_cfam_id =3D 0x221ef04980000000u= ll;=C2=A0=C2=A0/* P8 Murano DD2.1 > > */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->cores_mask =3D POWER8E_CORE_MASK; > > +=C2=A0=C2=A0=C2=A0=C2=A0k->core_pir =3D pnv_chip_core_pir_p8; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0dc->desc =3D "PowerNV Chip POWER8E"; > > =C2=A0} > > =C2=A0 > > @@ -292,6 +303,7 @@ static void > > pnv_chip_power8_class_init(ObjectClass *klass, void *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_type =3D PNV_CHIP_POWER8; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_cfam_id =3D 0x220ea04980000000u= ll; /* P8 Venice DD2.0 */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->cores_mask =3D POWER8_CORE_MASK; > > +=C2=A0=C2=A0=C2=A0=C2=A0k->core_pir =3D pnv_chip_core_pir_p8; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0dc->desc =3D "PowerNV Chip POWER8"; > > =C2=A0} > > =C2=A0 > > @@ -311,6 +323,7 @@ static void > > pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_type =3D PNV_CHIP_POWER8NVL; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_cfam_id =3D 0x120d304980000000u= ll;=C2=A0=C2=A0/* P8 Naples DD1.0 > > */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->cores_mask =3D POWER8_CORE_MASK; > > +=C2=A0=C2=A0=C2=A0=C2=A0k->core_pir =3D pnv_chip_core_pir_p8; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0dc->desc =3D "PowerNV Chip POWER8NVL"; > > =C2=A0} > > =C2=A0 > > @@ -330,6 +343,7 @@ static void > > pnv_chip_power9_class_init(ObjectClass *klass, void *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_type =3D PNV_CHIP_POWER9; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->chip_cfam_id =3D 0x100d104980000000u= ll; /* P9 Nimbus DD1.0 */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0k->cores_mask =3D POWER9_CORE_MASK; > > +=C2=A0=C2=A0=C2=A0=C2=A0k->core_pir =3D pnv_chip_core_pir_p9; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0dc->desc =3D "PowerNV Chip POWER9"; > > =C2=A0} > > =C2=A0 > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > > index cfc32586320f..2bd2294ac2a3 100644 > > --- a/include/hw/ppc/pnv.h > > +++ b/include/hw/ppc/pnv.h > > @@ -58,6 +58,7 @@ typedef struct PnvChipClass { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint64_t=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0c= ores_mask; > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0void (*realize)(PnvChip *dev, Error **e= rrp); > > +=C2=A0=C2=A0=C2=A0=C2=A0uint32_t (*core_pir)(PnvChip *chip, uint32_t= core_id); > > =C2=A0} PnvChipClass; > > =C2=A0 > > =C2=A0#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" >=20