From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bn5Og-0002lV-87 for qemu-devel@nongnu.org; Thu, 22 Sep 2016 10:54:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bn5Ob-0008Sq-85 for qemu-devel@nongnu.org; Thu, 22 Sep 2016 10:54:46 -0400 Received: from mail-sn1nam02on0067.outbound.protection.outlook.com ([104.47.36.67]:58578 helo=NAM02-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bn5Oa-0008Sc-UJ for qemu-devel@nongnu.org; Thu, 22 Sep 2016 10:54:41 -0400 From: Brijesh Singh Date: Thu, 22 Sep 2016 10:54:33 -0400 Message-ID: <147455607314.8519.15676884252094364037.stgit@brijesh-build-machine> In-Reply-To: <147455590865.8519.11191009507297313736.stgit@brijesh-build-machine> References: <147455590865.8519.11191009507297313736.stgit@brijesh-build-machine> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [RFC PATCH v2 16/16] i386: clear C-bit in SEV guest page table walk List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: ehabkost@redhat.com, crosthwaite.peter@gmail.com, armbru@redhat.com, mst@redhat.com, p.fedin@samsung.com, qemu-devel@nongnu.org, lcapitulino@redhat.com, pbonzini@redhat.com, rth@twiddle.net In SEV-enabled guest the physical addresses in page table will have C-bit set, we need to clear the C-bit when walking the page table. The C-bit position should be available in cpuid Fn8000_001f[EBX] Signed-off-by: Brijesh Singh --- target-i386/helper.c | 35 +++++++++++++++++++++++++++++------ target-i386/monitor.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 6 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 88fa4fa..b8e9c7b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" +#include "sysemu/sev.h" #include "kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" @@ -1006,6 +1007,22 @@ do_check_protect_pse36: return 1; } +static uint64_t get_me_mask(void) +{ + uint64_t me_mask = 0; + + /* In SEV guest page tables addresses will have memory encryption bit set, + * C-bit should be cleared while doing the page table walk. + */ + if (sev_enabled()) { + uint32_t pos; + pos = kvm_arch_get_supported_cpuid(kvm_state, 0x8000001f, 0, R_EBX); + me_mask = (1UL << pos); + } + + return ~me_mask; +} + hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { X86CPU *cpu = X86_CPU(cs); @@ -1014,6 +1031,12 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) uint64_t pte; uint32_t page_offset; int page_size; + uint64_t me_mask; + + me_mask = get_me_mask(); + + /* In SEV guest, CR3 will have memory encryption bit set, clear it */ + env->cr[3] &= me_mask; if (!(env->cr[0] & CR0_PG_MASK)) { pte = addr & env->a20_mask; @@ -1034,13 +1057,13 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) & env->a20_mask; - pml4e = ldq_phys_debug(cs, pml4e_addr); + pml4e = ldq_phys_debug(cs, pml4e_addr) & me_mask; if (!(pml4e & PG_PRESENT_MASK)) { return -1; } pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & env->a20_mask; - pdpe = ldq_phys_debug(cs, pdpe_addr); + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) { return -1; } @@ -1055,14 +1078,14 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & env->a20_mask; - pdpe = ldq_phys_debug(cs, pdpe_addr); + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) return -1; } pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & env->a20_mask; - pde = ldq_phys_debug(cs, pde_addr); + pde = ldq_phys_debug(cs, pde_addr) & me_mask; if (!(pde & PG_PRESENT_MASK)) { return -1; } @@ -1075,7 +1098,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & env->a20_mask; page_size = 4096; - pte = ldq_phys_debug(cs, pte_addr); + pte = ldq_phys_debug(cs, pte_addr) & me_mask; } if (!(pte & PG_PRESENT_MASK)) { return -1; @@ -1094,7 +1117,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } else { /* page directory entry */ pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask; - pte = ldl_phys_debug(cs, pte_addr); + pte = ldl_phys_debug(cs, pte_addr) & me_mask; if (!(pte & PG_PRESENT_MASK)) { return -1; } diff --git a/target-i386/monitor.c b/target-i386/monitor.c index 47d3c2d..0fe0c03 100644 --- a/target-i386/monitor.c +++ b/target-i386/monitor.c @@ -27,6 +27,7 @@ #include "monitor/hmp-target.h" #include "hw/i386/pc.h" #include "sysemu/kvm.h" +#include "sysemu/sev.h" #include "hmp.h" @@ -54,6 +55,22 @@ static void print_pte(Monitor *mon, hwaddr addr, pte & PG_RW_MASK ? 'W' : '-'); } +static uint64_t get_me_mask(void) +{ + uint64_t me_mask = 0; + + /* In SEV guest page tables addresses will have memory encryption bit set, + * C-bit should be cleared while doing the page table walk. + */ + if (sev_enabled()) { + uint32_t pos; + pos = kvm_arch_get_supported_cpuid(kvm_state, 0x8000001f, 0, R_EBX); + me_mask = (1UL << pos); + } + + return ~me_mask; +} + static void tlb_info_32(Monitor *mon, CPUArchState *env) { unsigned int l1, l2; @@ -127,15 +144,21 @@ static void tlb_info_64(Monitor *mon, CPUArchState *env) uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask = get_me_mask(); pml4_addr = env->cr[3] & 0x3fffffffff000ULL; + pml4_addr &= me_mask; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); + pml4e &= me_mask; pml4e = le64_to_cpu(pml4e); if (pml4e & PG_PRESENT_MASK) { pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); + pdpe &= me_mask; pdpe = le64_to_cpu(pdpe); if (pdpe & PG_PRESENT_MASK) { if (pdpe & PG_PSE_MASK) { @@ -147,6 +170,7 @@ static void tlb_info_64(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); + pde &= me_mask; pde = le64_to_cpu(pde); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -160,6 +184,7 @@ static void tlb_info_64(Monitor *mon, CPUArchState *env) cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); + pte &= me_mask; pte = le64_to_cpu(pte); if (pte & PG_PRESENT_MASK) { print_pte(mon, (l1 << 39) + @@ -331,18 +356,24 @@ static void mem_info_64(Monitor *mon, CPUArchState *env) uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask = get_me_mask(); pml4_addr = env->cr[3] & 0x3fffffffff000ULL; + pml4_addr &= me_mask; last_prot = 0; start = -1; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); + pml4e &= me_mask; pml4e = le64_to_cpu(pml4e); end = l1 << 39; if (pml4e & PG_PRESENT_MASK) { pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); + pdpe &= me_mask; pdpe = le64_to_cpu(pdpe); end = (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { @@ -356,6 +387,7 @@ static void mem_info_64(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); + pde &= me_mask; pde = le64_to_cpu(pde); end = (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { @@ -370,6 +402,7 @@ static void mem_info_64(Monitor *mon, CPUArchState *env) cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); + pte &= me_mask; pte = le64_to_cpu(pte); end = (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12);