From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnKmb-00018T-ER for qemu-devel@nongnu.org; Fri, 23 Sep 2016 03:20:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bnKmX-0001Bq-6o for qemu-devel@nongnu.org; Fri, 23 Sep 2016 03:20:28 -0400 Received: from mailapp02.imgtec.com ([217.156.133.132]:7200 helo=mailapp01.imgtec.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnKmX-0001Bm-0T for qemu-devel@nongnu.org; Fri, 23 Sep 2016 03:20:25 -0400 From: Leon Alrae Date: Fri, 23 Sep 2016 08:20:02 +0100 Message-ID: <1474615210-9006-2-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1474615210-9006-1-git-send-email-leon.alrae@imgtec.com> References: <1474615210-9006-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 1/9] target-mips: add 24KEc CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aurelien@aurel32.net, =?UTF-8?q?Andr=C3=A9=20Draszik?= From: Andr=C3=A9 Draszik Define a new CPU definition supporting 24KEc cores, similar to the existing 24Kc, but with added support for DSP instructions and MIPS16e (and without FPU). Signed-off-by: Andr=C3=A9 Draszik Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 39ed5c4..6ae23e4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] =3D .mmu_type =3D MMU_TYPE_R4000, }, { + .name =3D "24KEc", + .CP0_PRid =3D 0x00019600, + .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_I= A) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_D= A) | + (1 << CP0C1_CA), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_= VInt), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 4, + .SYNCI_Step =3D 32, + .CCRes =3D 2, + /* we have a DSP, but no FPU */ + .CP0_Status_rw_bitmask =3D 0x1378FF1F, + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .mmu_type =3D MMU_TYPE_R4000, + }, + { .name =3D "24Kf", .CP0_PRid =3D 0x00019300, .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | --=20 2.7.4