From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, aurelien@aurel32.net
Subject: [Qemu-devel] [PULL 2/9] target-mips: generate fences
Date: Fri, 23 Sep 2016 08:20:03 +0100 [thread overview]
Message-ID: <1474615210-9006-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1474615210-9006-1-git-send-email-leon.alrae@imgtec.com>
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-mips/translate.c | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index bab52cb..55c2ca0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13109,6 +13109,34 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t1);
}
+static void gen_sync(int stype)
+{
+ TCGBar tcg_mo = TCG_BAR_SC;
+
+ switch (stype) {
+ case 0x4: /* SYNC_WMB */
+ tcg_mo |= TCG_MO_ST_ST;
+ break;
+ case 0x10: /* SYNC_MB */
+ tcg_mo |= TCG_MO_ALL;
+ break;
+ case 0x11: /* SYNC_ACQUIRE */
+ tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;
+ break;
+ case 0x12: /* SYNC_RELEASE */
+ tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;
+ break;
+ case 0x13: /* SYNC_RMB */
+ tcg_mo |= TCG_MO_LD_LD;
+ break;
+ default:
+ tcg_mo |= TCG_MO_ALL;
+ break;
+ }
+
+ tcg_gen_mb(tcg_mo);
+}
+
static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
{
int extension = (ctx->opcode >> 6) & 0x3f;
@@ -13384,7 +13412,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case 0x2d:
switch (minor) {
case SYNC:
- /* NOP */
+ gen_sync(extract32(ctx->opcode, 16, 5));
break;
case SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL);
@@ -17201,7 +17229,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SYNC:
check_insn(ctx, ISA_MIPS2);
- /* Treat as NOP. */
+ gen_sync(extract32(ctx->opcode, 6, 5));
break;
#if defined(TARGET_MIPS64)
--
2.7.4
next prev parent reply other threads:[~2016-09-23 7:20 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-23 7:20 [Qemu-devel] [PULL 0/9] target-mips queue Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 1/9] target-mips: add 24KEc CPU definition Leon Alrae
2016-09-23 7:20 ` Leon Alrae [this message]
2016-09-23 7:20 ` [Qemu-devel] [PULL 3/9] linux-user: Fix TARGET_SIOCATMARK definition for Mips Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 4/9] linux-user: Fix TARGET_F_GETOWN " Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 5/9] linux-user: Fix structure target_flock " Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 6/9] linux-user: Fix structure target_semid64_ds " Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 7/9] linux-user: Fix certain argument alignment cases for Mips64 Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 8/9] linux-user: Add missing TARGET_EDQUOT error code for Mips Leon Alrae
2016-09-23 7:20 ` [Qemu-devel] [PULL 9/9] linux-user: Add missing Mips syscalls items in strace.list Leon Alrae
2016-09-23 15:15 ` [Qemu-devel] [PULL 0/9] target-mips queue Peter Maydell
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