From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:55208)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <benh@kernel.crashing.org>) id 1bopSJ-0007W0-GV
	for qemu-devel@nongnu.org; Tue, 27 Sep 2016 06:17:44 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <benh@kernel.crashing.org>) id 1bopSF-0005ql-A4
	for qemu-devel@nongnu.org; Tue, 27 Sep 2016 06:17:42 -0400
Message-ID: <1474971446.2857.279.camel@kernel.crashing.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 27 Sep 2016 20:17:26 +1000
In-Reply-To: <c520587b-db61-6ca5-dc0a-7cf88c750e07@kaod.org>
References: <1473943560-14846-1-git-send-email-clg@kaod.org>
	<1473943560-14846-8-git-send-email-clg@kaod.org>
	<20160921060845.GC20488@umbus>
	<c520587b-db61-6ca5-dc0a-7cf88c750e07@kaod.org>
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Subject: Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>, David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On Tue, 2016-09-27 at 11:10 +0200, C=C3=A9dric Le Goater wrote:
> >=C2=A0
> > >=20
> > > +=C2=A0=C2=A0=C2=A0=C2=A0PowerPCCPU *cpu =3D POWERPC_CPU(cs);
> > > +=C2=A0=C2=A0=C2=A0=C2=A0CPUPPCState *env =3D &cpu->env;
> > > +
> > > +=C2=A0=C2=A0=C2=A0=C2=A0cpu_synchronize_state(cs);
> > > +=C2=A0=C2=A0=C2=A0=C2=A0env->spr[SPR_HMER] |=3D hmer_bits;
> > > +
> > > +=C2=A0=C2=A0=C2=A0=C2=A0/* XXX Need a CPU helper to set HMER, also=
 handle gneeration
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* of HMIs
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/
>=20
> Ben,=C2=A0
>=20
> The CPU helper would be to replicate the value of the SPR_HMER in all
> the threads of the core I guess ?=C2=A0

Nope, those HMER bits are per-thread afaik, but I dislike having a
device whack at CPU state...

Also when we do PR KVM of powernv, we'll want to sync the SPR with KVM
I suppose.

Cheers,
Ben.
=C2=A0