From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bor6X-0000zu-BH for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bor6R-0002kA-IY for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:21 -0400 Received: from 2.mo178.mail-out.ovh.net ([46.105.39.61]:42642) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bor6R-0002jr-CR for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:15 -0400 Received: from player169.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 7D2EFFFA24B for ; Tue, 27 Sep 2016 14:03:14 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Tue, 27 Sep 2016 13:57:36 +0200 Message-Id: <1474977462-28032-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 0/6] aspeed: add support for the ast2500 SMC controllers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Peter Crosthwaite Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Hello, The Aspeed AST2500 has one 'SPI' controller for the BMC firmware and two 'SPI' for the host firmware. All controllers have now the same set of registers compatible with the AST2400 'FMC' controller and the legacy 'SMC' controller is fully gone. This serie adds support for the second SPI controller and for the segment registers which are used to configure the mapping of each flash module in the SoC address space. Thanks, C.=20 C=C3=A9dric Le Goater (6): aspeed: rename smc object to fmc aspeed: move the flash module mapping address under the controller definition aspeed: extend the number of host SPI controllers aspeed: add support for the AST2500 SoC SMC controllers aspeed: create mapping regions for the maximum number of slaves aspeed: add support for the SMC segment registers hw/arm/aspeed.c | 4 +- hw/arm/aspeed_soc.c | 74 +++++++++++------ hw/ssi/aspeed_smc.c | 194 ++++++++++++++++++++++++++++++++++++++= +++--- include/hw/arm/aspeed_soc.h | 10 ++- include/hw/ssi/aspeed_smc.h | 3 +- 5 files changed, 241 insertions(+), 44 deletions(-) --=20 2.7.4