From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bor72-0001PG-J5 for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bor6x-0002w8-O6 for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:51 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:60686) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bor6x-0002vs-IY for qemu-devel@nongnu.org; Tue, 27 Sep 2016 08:03:47 -0400 Received: from player169.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 16C2DFFA237 for ; Tue, 27 Sep 2016 14:03:47 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Tue, 27 Sep 2016 13:57:41 +0200 Message-Id: <1474977462-28032-6-git-send-email-clg@kaod.org> In-Reply-To: <1474977462-28032-1-git-send-email-clg@kaod.org> References: <1474977462-28032-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 5/6] aspeed: create mapping regions for the maximum number of slaves List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Peter Crosthwaite Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= The SMC controller on the Aspeed SoC has a set of registers to configure the mapping of each flash module in the SoC address space. These mapping windows are configurable even though no SPI slave is attached to the controller. Also rewrite a bit the comments in the code on this topic. Signed-off-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 21943f4e5dfa..ecf39ccfde0e 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -417,12 +417,15 @@ static void aspeed_smc_realize(DeviceState *dev, Er= ror **errp) =20 aspeed_smc_reset(dev); =20 + /* The memory region for the controller registers */ memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, s->ctrl->name, ASPEED_SMC_R_MAX * 4); sysbus_init_mmio(sbd, &s->mmio); =20 /* - * Memory region where flash modules are remapped + * The container memory region representing the address space + * window in which the flash modules are mapped. The size and + * address depends on the SoC model and controller type. */ snprintf(name, sizeof(name), "%s.flash", s->ctrl->name); =20 @@ -431,9 +434,16 @@ static void aspeed_smc_realize(DeviceState *dev, Err= or **errp) s->ctrl->flash_window_size); sysbus_init_mmio(sbd, &s->mmio_flash); =20 - s->flashes =3D g_new0(AspeedSMCFlash, s->num_cs); + s->flashes =3D g_new0(AspeedSMCFlash, s->ctrl->max_slaves); =20 - for (i =3D 0; i < s->num_cs; ++i) { + /* + * Let's create a sub memory region for each possible slave. All + * have a configurable memory segment in the overall flash mapping + * window of the controller but, there is not necessarily a flash + * module behind to handle the memory accesses. This depends on + * the board configuration. + */ + for (i =3D 0; i < s->ctrl->max_slaves; ++i) { AspeedSMCFlash *fl =3D &s->flashes[i]; =20 snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i); --=20 2.7.4