From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpJoE-0006Tc-Km for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bpJo9-0005Ek-JG for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:22 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:40772 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpJo9-0005DV-E9 for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:17 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8SIbluS055282 for ; Wed, 28 Sep 2016 14:42:15 -0400 Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) by mx0a-001b2d01.pphosted.com with ESMTP id 25rc98rms3-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 28 Sep 2016 14:42:15 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 29 Sep 2016 04:42:12 +1000 From: Nikunj A Dadhania Date: Thu, 29 Sep 2016 00:11:51 +0530 Message-Id: <1475088120-20244-1-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v5 0/9] POWER9 TCG enablements - part4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org This series contains 7 new instructions for POWER9 ISA3.0 Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x. GCC was adding epilogue for every VSX instructions causing change in behaviour. For testing the load vector instructions used mfvsrld/mfvsrd for loading vsr to register. And for testing store vector, used mtvsrdd instructions. This helped in getting rid of the epilogue added by gcc. Patches: 01: mfvsrld: Move From VSR Lower Doubleword 02: mtvsrdd: Move To VSR Double Doubleword 03: mtvsrws: Move To VSR Word & Splat 05: lxvw4x: improve implementation 05: stxv4x: improve implementation 06: lxvh8x: Load VSX Vector Halfword*8 07: stxvh8x: Store VSX Vector Halfword*8 08: lxvb16x: Load VSX Vector Byte*16 09: stxvb16x: Store VSX Vector Byte*16 Changelog: v4: * Added gen_bswap16x8 inline for lxvh8x and stxvh8x in tcg * Dropped helper_bswap16x4 * Use temporaries in stxvh8x and not clobber the register v3: * Added 3 new VSR instructions. * Fixed all the vector load/store instructions for BE/LE. * Added detailed commit messages to patches. * Dropped deposit32x2 and implemented it using tcg ops v2: * Fix lxvw4x/stxv4x translation as LE/BE were both similar one in tcg and other as helper * Rename bswap32x2 to deposit32x2 as it does not need to swap content(32bit) * stxvh8x had a bug as David suggested. v1: * More load/store cleanups in byte reverse routines * ld64/st64 converted to newer macro and updated call sites * Cleanup load with reservation and store conditional * Return invalid random for darn instruction v0: * darn - read /dev/random to get the random number * xxspltib - make is PPC64 only * Consolidate load/store operations and use macros to generate qemu_st/ld * Simplify load/store vsx endian manipulation Nikunj A Dadhania (6): target-ppc: improve lxvw4x implementation target-ppc: improve stxvw4x implementation target-ppc: add lxvh8x instruction target-ppc: add stxvh8x instruction target-ppc: add lxvb16x instruction target-ppc: add stxvb16x instruction Ravi Bangoria (3): target-ppc: Implement mfvsrld instruction target-ppc: Implement mtvsrdd instruction target-ppc: Implement mtvsrws instruction target-ppc/translate/vsx-impl.inc.c | 238 ++++++++++++++++++++++++++++++++---- target-ppc/translate/vsx-ops.inc.c | 7 ++ 2 files changed, 221 insertions(+), 24 deletions(-) -- 2.7.4