From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpJoQ-0006Xo-1P for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bpJoJ-0005K6-VC for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:33 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:41591 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpJoJ-0005Jp-Pf for qemu-devel@nongnu.org; Wed, 28 Sep 2016 14:42:27 -0400 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8SIgP5I084338 for ; Wed, 28 Sep 2016 14:42:27 -0400 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0b-001b2d01.pphosted.com with ESMTP id 25rgngqqhv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 28 Sep 2016 14:42:27 -0400 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 29 Sep 2016 04:42:23 +1000 From: Nikunj A Dadhania Date: Thu, 29 Sep 2016 00:11:54 +0530 In-Reply-To: <1475088120-20244-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1475088120-20244-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1475088120-20244-4-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org, Ravi Bangoria From: Ravi Bangoria mtvsrws: Move To VSR Word & Splat Signed-off-by: Ravi Bangoria Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson --- target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++ target-ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 24 insertions(+) diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index c4c50dd..fa8240f 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -257,6 +257,29 @@ static void gen_mtvsrdd(DisasContext *ctx) tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]); } +static void gen_mtvsrws(DisasContext *ctx) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + + if (xT(ctx->opcode) < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode))); + + tcg_temp_free_i64(t0); +} + #endif static void gen_xxpermdi(DisasContext *ctx) diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 1287973..d5f5b87 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -24,6 +24,7 @@ GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300), #endif #define GEN_XX1FORM(name, opc2, opc3, fl2) \ -- 2.7.4