From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxdk-0007WP-GA for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:26:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bqxdh-0003c0-6t for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:26:20 -0400 Received: from 5.mo68.mail-out.ovh.net ([46.105.62.179]:59154) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxdg-0003bY-Qq for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:26:17 -0400 Received: from player711.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 3817410005AC for ; Mon, 3 Oct 2016 09:26:16 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 3 Oct 2016 09:24:47 +0200 Message-Id: <1475479496-16158-12-git-send-email-clg@kaod.org> In-Reply-To: <1475479496-16158-1-git-send-email-clg@kaod.org> References: <1475479496-16158-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v4 11/20] ppc/xics: Split ICS into ics-base and ics class List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Cedric Le Goater , Nikunj A Dadhania From: Benjamin Herrenschmidt The existing implementation remains same and ics-base is introduced. The type name "ics" is retained, and all the related functions renamed as ics_simple_* This will allow different implementations for the source controllers such as the MSI support of PHB3 on Power8 which uses in-memory state tables for example. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson [ clg: added ICS_BASE_GET_CLASS and related fixes, based on : http://patchwork.ozlabs.org/patch/646010/ ] Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/trace-events | 10 ++-- hw/intc/xics.c | 150 +++++++++++++++++++++++++++++++-------------= ------ hw/intc/xics_kvm.c | 12 ++-- hw/intc/xics_spapr.c | 30 +++++----- include/hw/ppc/xics.h | 27 +++++---- 5 files changed, 138 insertions(+), 91 deletions(-) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index aa342a86fa6c..a367b46b1c20 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -50,12 +50,12 @@ xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr)= "icp_accept: XIRR %#"PRIx3 xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) "icp_eoi: ser= ver %d given XIRR %#"PRIx32" new XIRR %#"PRIx32 xics_icp_irq(int server, int nr, uint8_t priority) "cpu %d trying to del= iver irq %#"PRIx32" priority %#x" xics_icp_raise(uint32_t xirr, uint8_t pending_priority) "raising IRQ new= XIRR=3D%#x new pending priority=3D%#x" -xics_set_irq_msi(int srcno, int nr) "set_irq_msi: srcno %d [irq %#x]" +xics_ics_simple_set_irq_msi(int srcno, int nr) "set_irq_msi: srcno %d [i= rq %#x]" xics_masked_pending(void) "set_irq_msi: masked pending" -xics_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [irq %#x]" -xics_ics_write_xive(int nr, int srcno, int server, uint8_t priority) "ic= s_write_xive: irq %#x [src %d] server %#x prio %#x" -xics_ics_reject(int nr, int srcno) "reject irq %#x [src %d]" -xics_ics_eoi(int nr) "ics_eoi: irq %#x" +xics_ics_simple_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [i= rq %#x]" +xics_ics_simple_write_xive(int nr, int srcno, int server, uint8_t priori= ty) "ics_write_xive: irq %#x [src %d] server %#x prio %#x" +xics_ics_simple_reject(int nr, int srcno) "reject irq %#x [src %d]" +xics_ics_simple_eoi(int nr) "ics_eoi: irq %#x" xics_alloc(int irq) "irq %d" xics_alloc_block(int first, int num, bool lsi, int align) "first irq %d,= %d irqs, lsi=3D%d, alignnum %d" xics_ics_free(int src, int irq, int num) "Source#%d, first irq %d, %d ir= qs" diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 433af93254fb..f40b00003a45 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -213,9 +213,32 @@ static const TypeInfo xics_common_info =3D { #define XISR(ss) (((ss)->xirr) & XISR_MASK) #define CPPR(ss) (((ss)->xirr) >> 24) =20 -static void ics_reject(ICSState *ics, int nr); -static void ics_resend(ICSState *ics); -static void ics_eoi(ICSState *ics, int nr); +static void ics_reject(ICSState *ics, uint32_t nr) +{ + ICSStateClass *k =3D ICS_BASE_GET_CLASS(ics); + + if (k->reject) { + k->reject(ics, nr); + } +} + +static void ics_resend(ICSState *ics) +{ + ICSStateClass *k =3D ICS_BASE_GET_CLASS(ics); + + if (k->resend) { + k->resend(ics); + } +} + +static void ics_eoi(ICSState *ics, int nr) +{ + ICSStateClass *k =3D ICS_BASE_GET_CLASS(ics); + + if (k->eoi) { + k->eoi(ics, nr); + } +} =20 static void icp_check_ipi(ICPState *ss) { @@ -418,7 +441,7 @@ static const TypeInfo icp_info =3D { /* * ICS: Source layer */ -static void resend_msi(ICSState *ics, int srcno) +static void ics_simple_resend_msi(ICSState *ics, int srcno) { ICSIRQState *irq =3D ics->irqs + srcno; =20 @@ -431,7 +454,7 @@ static void resend_msi(ICSState *ics, int srcno) } } =20 -static void resend_lsi(ICSState *ics, int srcno) +static void ics_simple_resend_lsi(ICSState *ics, int srcno) { ICSIRQState *irq =3D ics->irqs + srcno; =20 @@ -443,11 +466,11 @@ static void resend_lsi(ICSState *ics, int srcno) } } =20 -static void set_irq_msi(ICSState *ics, int srcno, int val) +static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val) { ICSIRQState *irq =3D ics->irqs + srcno; =20 - trace_xics_set_irq_msi(srcno, srcno + ics->offset); + trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset); =20 if (val) { if (irq->priority =3D=3D 0xff) { @@ -459,31 +482,31 @@ static void set_irq_msi(ICSState *ics, int srcno, i= nt val) } } =20 -static void set_irq_lsi(ICSState *ics, int srcno, int val) +static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val) { ICSIRQState *irq =3D ics->irqs + srcno; =20 - trace_xics_set_irq_lsi(srcno, srcno + ics->offset); + trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset); if (val) { irq->status |=3D XICS_STATUS_ASSERTED; } else { irq->status &=3D ~XICS_STATUS_ASSERTED; } - resend_lsi(ics, srcno); + ics_simple_resend_lsi(ics, srcno); } =20 -static void ics_set_irq(void *opaque, int srcno, int val) +static void ics_simple_set_irq(void *opaque, int srcno, int val) { ICSState *ics =3D (ICSState *)opaque; =20 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { - set_irq_lsi(ics, srcno, val); + ics_simple_set_irq_lsi(ics, srcno, val); } else { - set_irq_msi(ics, srcno, val); + ics_simple_set_irq_msi(ics, srcno, val); } } =20 -static void write_xive_msi(ICSState *ics, int srcno) +static void ics_simple_write_xive_msi(ICSState *ics, int srcno) { ICSIRQState *irq =3D ics->irqs + srcno; =20 @@ -496,35 +519,35 @@ static void write_xive_msi(ICSState *ics, int srcno= ) icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); } =20 -static void write_xive_lsi(ICSState *ics, int srcno) +static void ics_simple_write_xive_lsi(ICSState *ics, int srcno) { - resend_lsi(ics, srcno); + ics_simple_resend_lsi(ics, srcno); } =20 -void ics_write_xive(ICSState *ics, int nr, int server, - uint8_t priority, uint8_t saved_priority) +void ics_simple_write_xive(ICSState *ics, int srcno, int server, + uint8_t priority, uint8_t saved_priority) { - int srcno =3D nr - ics->offset; ICSIRQState *irq =3D ics->irqs + srcno; =20 irq->server =3D server; irq->priority =3D priority; irq->saved_priority =3D saved_priority; =20 - trace_xics_ics_write_xive(nr, srcno, server, priority); + trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server, + priority); =20 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { - write_xive_lsi(ics, srcno); + ics_simple_write_xive_lsi(ics, srcno); } else { - write_xive_msi(ics, srcno); + ics_simple_write_xive_msi(ics, srcno); } } =20 -static void ics_reject(ICSState *ics, int nr) +static void ics_simple_reject(ICSState *ics, uint32_t nr) { ICSIRQState *irq =3D ics->irqs + nr - ics->offset; =20 - trace_xics_ics_reject(nr, nr - ics->offset); + trace_xics_ics_simple_reject(nr, nr - ics->offset); if (irq->flags & XICS_FLAGS_IRQ_MSI) { irq->status |=3D XICS_STATUS_REJECTED; } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { @@ -532,35 +555,35 @@ static void ics_reject(ICSState *ics, int nr) } } =20 -static void ics_resend(ICSState *ics) +static void ics_simple_resend(ICSState *ics) { int i; =20 for (i =3D 0; i < ics->nr_irqs; i++) { /* FIXME: filter by server#? */ if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { - resend_lsi(ics, i); + ics_simple_resend_lsi(ics, i); } else { - resend_msi(ics, i); + ics_simple_resend_msi(ics, i); } } } =20 -static void ics_eoi(ICSState *ics, int nr) +static void ics_simple_eoi(ICSState *ics, uint32_t nr) { int srcno =3D nr - ics->offset; ICSIRQState *irq =3D ics->irqs + srcno; =20 - trace_xics_ics_eoi(nr); + trace_xics_ics_simple_eoi(nr); =20 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { irq->status &=3D ~XICS_STATUS_SENT; } } =20 -static void ics_reset(DeviceState *dev) +static void ics_simple_reset(DeviceState *dev) { - ICSState *ics =3D ICS(dev); + ICSState *ics =3D ICS_SIMPLE(dev); int i; uint8_t flags[ics->nr_irqs]; =20 @@ -577,7 +600,7 @@ static void ics_reset(DeviceState *dev) } } =20 -static int ics_post_load(ICSState *ics, int version_id) +static int ics_simple_post_load(ICSState *ics, int version_id) { int i; =20 @@ -588,20 +611,20 @@ static int ics_post_load(ICSState *ics, int version= _id) return 0; } =20 -static void ics_dispatch_pre_save(void *opaque) +static void ics_simple_dispatch_pre_save(void *opaque) { ICSState *ics =3D opaque; - ICSStateClass *info =3D ICS_GET_CLASS(ics); + ICSStateClass *info =3D ICS_BASE_GET_CLASS(ics); =20 if (info->pre_save) { info->pre_save(ics); } } =20 -static int ics_dispatch_post_load(void *opaque, int version_id) +static int ics_simple_dispatch_post_load(void *opaque, int version_id) { ICSState *ics =3D opaque; - ICSStateClass *info =3D ICS_GET_CLASS(ics); + ICSStateClass *info =3D ICS_BASE_GET_CLASS(ics); =20 if (info->post_load) { return info->post_load(ics, version_id); @@ -610,7 +633,7 @@ static int ics_dispatch_post_load(void *opaque, int v= ersion_id) return 0; } =20 -static const VMStateDescription vmstate_ics_irq =3D { +static const VMStateDescription vmstate_ics_simple_irq =3D { .name =3D "ics/irq", .version_id =3D 2, .minimum_version_id =3D 1, @@ -624,59 +647,71 @@ static const VMStateDescription vmstate_ics_irq =3D= { }, }; =20 -static const VMStateDescription vmstate_ics =3D { +static const VMStateDescription vmstate_ics_simple =3D { .name =3D "ics", .version_id =3D 1, .minimum_version_id =3D 1, - .pre_save =3D ics_dispatch_pre_save, - .post_load =3D ics_dispatch_post_load, + .pre_save =3D ics_simple_dispatch_pre_save, + .post_load =3D ics_simple_dispatch_post_load, .fields =3D (VMStateField[]) { /* Sanity check */ VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), =20 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, - vmstate_ics_irq, ICSIRQStat= e), + vmstate_ics_simple_irq, + ICSIRQState), VMSTATE_END_OF_LIST() }, }; =20 -static void ics_initfn(Object *obj) +static void ics_simple_initfn(Object *obj) { - ICSState *ics =3D ICS(obj); + ICSState *ics =3D ICS_SIMPLE(obj); =20 ics->offset =3D XICS_IRQ_BASE; } =20 -static void ics_realize(DeviceState *dev, Error **errp) +static void ics_simple_realize(DeviceState *dev, Error **errp) { - ICSState *ics =3D ICS(dev); + ICSState *ics =3D ICS_SIMPLE(dev); =20 if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); return; } ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); - ics->qirqs =3D qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); + ics->qirqs =3D qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_i= rqs); } =20 -static void ics_class_init(ObjectClass *klass, void *data) +static void ics_simple_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - ICSStateClass *isc =3D ICS_CLASS(klass); + ICSStateClass *isc =3D ICS_BASE_CLASS(klass); =20 - dc->realize =3D ics_realize; - dc->vmsd =3D &vmstate_ics; - dc->reset =3D ics_reset; - isc->post_load =3D ics_post_load; + dc->realize =3D ics_simple_realize; + dc->vmsd =3D &vmstate_ics_simple; + dc->reset =3D ics_simple_reset; + isc->post_load =3D ics_simple_post_load; + isc->reject =3D ics_simple_reject; + isc->resend =3D ics_simple_resend; + isc->eoi =3D ics_simple_eoi; } =20 -static const TypeInfo ics_info =3D { - .name =3D TYPE_ICS, +static const TypeInfo ics_simple_info =3D { + .name =3D TYPE_ICS_SIMPLE, + .parent =3D TYPE_ICS_BASE, + .instance_size =3D sizeof(ICSState), + .class_init =3D ics_simple_class_init, + .class_size =3D sizeof(ICSStateClass), + .instance_init =3D ics_simple_initfn, +}; + +static const TypeInfo ics_base_info =3D { + .name =3D TYPE_ICS_BASE, .parent =3D TYPE_DEVICE, + .abstract =3D true, .instance_size =3D sizeof(ICSState), - .class_init =3D ics_class_init, .class_size =3D sizeof(ICSStateClass), - .instance_init =3D ics_initfn, }; =20 /* @@ -716,7 +751,8 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool = lsi) static void xics_register_types(void) { type_register_static(&xics_common_info); - type_register_static(&ics_info); + type_register_static(&ics_simple_info); + type_register_static(&ics_base_info); type_register_static(&icp_info); } =20 diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 843905cfbd37..9c2f198fd142 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -272,7 +272,7 @@ static void ics_kvm_set_irq(void *opaque, int srcno, = int val) =20 static void ics_kvm_reset(DeviceState *dev) { - ICSState *ics =3D ICS(dev); + ICSState *ics =3D ICS_SIMPLE(dev); int i; uint8_t flags[ics->nr_irqs]; =20 @@ -293,7 +293,7 @@ static void ics_kvm_reset(DeviceState *dev) =20 static void ics_kvm_realize(DeviceState *dev, Error **errp) { - ICSState *ics =3D ICS(dev); + ICSState *ics =3D ICS_SIMPLE(dev); =20 if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); @@ -306,7 +306,7 @@ static void ics_kvm_realize(DeviceState *dev, Error *= *errp) static void ics_kvm_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - ICSStateClass *icsc =3D ICS_CLASS(klass); + ICSStateClass *icsc =3D ICS_BASE_CLASS(klass); =20 dc->realize =3D ics_kvm_realize; dc->reset =3D ics_kvm_reset; @@ -315,8 +315,8 @@ static void ics_kvm_class_init(ObjectClass *klass, vo= id *data) } =20 static const TypeInfo ics_kvm_info =3D { - .name =3D TYPE_KVM_ICS, - .parent =3D TYPE_ICS, + .name =3D TYPE_ICS_KVM, + .parent =3D TYPE_ICS_SIMPLE, .instance_size =3D sizeof(ICSState), .class_init =3D ics_kvm_class_init, }; @@ -488,7 +488,7 @@ static void xics_kvm_initfn(Object *obj) XICSState *xics =3D XICS_COMMON(obj); ICSState *ics; =20 - ics =3D ICS(object_new(TYPE_KVM_ICS)); + ics =3D ICS_SIMPLE(object_new(TYPE_ICS_KVM)); object_property_add_child(obj, "ics", OBJECT(ics), NULL); ics->xics =3D xics; QLIST_INSERT_HEAD(&xics->ics, ics, list); diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 0b0845d6280f..e8d0623c2cb5 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -114,7 +114,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, uint32_t nret, target_ulong rets) { ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); - uint32_t nr, server, priority; + uint32_t nr, srcno, server, priority; =20 if ((nargs !=3D 3) || (nret !=3D 1)) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -135,7 +135,8 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, return; } =20 - ics_write_xive(ics, nr, server, priority, priority); + srcno =3D nr - ics->offset; + ics_simple_write_xive(ics, srcno, server, priority, priority); =20 rtas_st(rets, 0, RTAS_OUT_SUCCESS); } @@ -146,7 +147,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, uint32_t nret, target_ulong rets) { ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); - uint32_t nr; + uint32_t nr, srcno; =20 if ((nargs !=3D 1) || (nret !=3D 3)) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -165,8 +166,9 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, } =20 rtas_st(rets, 0, RTAS_OUT_SUCCESS); - rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); - rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); + srcno =3D nr - ics->offset; + rtas_st(rets, 1, ics->irqs[srcno].server); + rtas_st(rets, 2, ics->irqs[srcno].priority); } =20 static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, @@ -175,7 +177,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachin= eState *spapr, uint32_t nret, target_ulong rets) { ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); - uint32_t nr; + uint32_t nr, srcno; =20 if ((nargs !=3D 1) || (nret !=3D 1)) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -193,8 +195,9 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachin= eState *spapr, return; } =20 - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, - ics->irqs[nr - ics->offset].priority); + srcno =3D nr - ics->offset; + ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff, + ics->irqs[srcno].priority); =20 rtas_st(rets, 0, RTAS_OUT_SUCCESS); } @@ -205,7 +208,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachine= State *spapr, uint32_t nret, target_ulong rets) { ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); - uint32_t nr; + uint32_t nr, srcno; =20 if ((nargs !=3D 1) || (nret !=3D 1)) { rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); @@ -223,9 +226,10 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachin= eState *spapr, return; } =20 - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, - ics->irqs[nr - ics->offset].saved_priority, - ics->irqs[nr - ics->offset].saved_priority); + srcno =3D nr - ics->offset; + ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, + ics->irqs[srcno].saved_priority, + ics->irqs[srcno].saved_priority); =20 rtas_st(rets, 0, RTAS_OUT_SUCCESS); } @@ -307,7 +311,7 @@ static void xics_spapr_initfn(Object *obj) XICSState *xics =3D XICS_SPAPR(obj); ICSState *ics; =20 - ics =3D ICS(object_new(TYPE_ICS)); + ics =3D ICS_SIMPLE(object_new(TYPE_ICS_SIMPLE)); object_property_add_child(obj, "ics", OBJECT(ics), NULL); ics->xics =3D xics; QLIST_INSERT_HEAD(&xics->ics, ics, list); diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index e49a2dab934a..66ae55ded387 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -119,22 +119,29 @@ struct ICPState { bool cap_irq_xics_enabled; }; =20 -#define TYPE_ICS "ics" -#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) +#define TYPE_ICS_BASE "ics-base" +#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) =20 -#define TYPE_KVM_ICS "icskvm" -#define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS) +/* Retain ics for sPAPR for migration from existing sPAPR guests */ +#define TYPE_ICS_SIMPLE "ics" +#define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) =20 -#define ICS_CLASS(klass) \ - OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) -#define ICS_GET_CLASS(obj) \ - OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) +#define TYPE_ICS_KVM "icskvm" +#define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) + +#define ICS_BASE_CLASS(klass) \ + OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) +#define ICS_BASE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) =20 struct ICSStateClass { DeviceClass parent_class; =20 void (*pre_save)(ICSState *s); int (*post_load)(ICSState *s, int version_id); + void (*reject)(ICSState *s, uint32_t irq); + void (*resend)(ICSState *s); + void (*eoi)(ICSState *s, uint32_t irq); }; =20 struct ICSState { @@ -191,8 +198,8 @@ uint32_t icp_accept(ICPState *ss); uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); void icp_eoi(XICSState *icp, int server, uint32_t xirr); =20 -void ics_write_xive(ICSState *ics, int nr, int server, - uint8_t priority, uint8_t saved_priority); +void ics_simple_write_xive(ICSState *ics, int nr, int server, + uint8_t priority, uint8_t saved_priority); =20 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); =20 --=20 2.7.4