From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxeP-0008Bo-D1 for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:27:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bqxeO-0003yX-5G for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:27:01 -0400 Received: from 10.mo68.mail-out.ovh.net ([46.105.79.203]:49945) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxeN-0003y6-TX for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:27:00 -0400 Received: from player711.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 6FD5210005B2 for ; Mon, 3 Oct 2016 09:26:59 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 3 Oct 2016 09:24:55 +0200 Message-Id: <1475479496-16158-20-git-send-email-clg@kaod.org> In-Reply-To: <1475479496-16158-1-git-send-email-clg@kaod.org> References: <1475479496-16158-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Cedric Le Goater From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.7 - ported on latest PowerNV patchset (v3) ] Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 18 +++++++++++++++++- hw/ppc/pnv_lpc.c | 47 ++++++++++++++++++++++++++++++++++++++++++= +++-- include/hw/ppc/pnv_lpc.h | 7 +++++++ 3 files changed, 69 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e805e97d4d87..5b70ccf66fac 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -340,7 +340,17 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaqu= e, int n, int level) =20 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) { - /* XXX TODO */ + PnvLpcController *lpc =3D opaque; + + if (n >=3D ISA_NUM_IRQS) { + return; + } + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |=3D LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } } =20 static ISABus *pnv_isa_create(PnvChip *chip) @@ -656,6 +666,12 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* + * The LPC controller needs PSI to generate interrupts + */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } =20 static void pnv_chip_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 210cc1cff167..8b78b0a1e414 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -249,6 +249,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq =3D false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs =3D lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq =3D (irqs !=3D 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |=3D OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &=3D ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D = 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc =3D opaque; @@ -299,12 +327,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr,= uint64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -362,14 +393,15 @@ static void opb_master_write(void *opaque, hwaddr a= ddr, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -397,6 +429,8 @@ static const MemoryRegionOps opb_master_ops =3D { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); + Object *obj; + Error *error =3D NULL; =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -440,6 +474,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error = **errp) memory_region_init_io(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE << 3); + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975aa..fc348dca50ca 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,9 +23,13 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) =20 +typedef struct PnvPsiController PnvPsiController; + typedef struct PnvLpcController { DeviceState parent; =20 + PnvPsiController *psi; + uint64_t eccb_stat_reg; uint32_t eccb_data_reg; =20 @@ -64,4 +68,7 @@ typedef struct PnvLpcController { MemoryRegion xscom_regs; } PnvLpcController; =20 +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to .= .. */ +void pnv_lpc_eval_irqs(PnvLpcController *lpc); + #endif /* _PPC_PNV_LPC_H */ --=20 2.7.4