From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxd5-0006w9-Dn for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:25:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bqxd1-0003Fv-NL for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:25:39 -0400 Received: from 9.mo68.mail-out.ovh.net ([46.105.78.111]:40995) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bqxd1-0003FO-8r for qemu-devel@nongnu.org; Mon, 03 Oct 2016 03:25:35 -0400 Received: from player711.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 72D0410005A9 for ; Mon, 3 Oct 2016 09:25:34 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 3 Oct 2016 09:24:40 +0200 Message-Id: <1475479496-16158-5-git-send-email-clg@kaod.org> In-Reply-To: <1475479496-16158-1-git-send-email-clg@kaod.org> References: <1475479496-16158-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Cedric Le Goater The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9 and P8 have some differences in the CPU PIR encoding. Signed-off-by: C=C3=A9dric Le Goater --- Changes since v3 : - added a couple more comments on the bits definition =20 hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fc930be94f53..758c849702a0 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -239,6 +239,32 @@ static void ppc_powernv_init(MachineState *machine) g_free(chip_typename); } =20 +/* + * 0:21 Reserved - Read as zeros + * 22:24 Chip ID + * 25:28 Core number + * 29:31 Thread ID + */ +static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 7) | (core_id << 3); +} + +/* + * 0:48 Reserved - Read as zeroes + * 49:52 Node ID + * 53:55 Chip ID + * 56 Reserved - Read as zero + * 57:61 Core number + * 62:63 Thread ID + * + * We only care about the lower bits. uint32_t is fine for the moment. + */ +static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 8) | (core_id << 2); +} + /* Allowed core identifiers on a POWER8 Processor Chip : * * @@ -274,6 +300,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8E"; } =20 @@ -293,6 +320,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8"; } =20 @@ -312,6 +340,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p8; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 @@ -331,6 +360,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask =3D POWER9_CORE_MASK; + k->core_pir =3D pnv_chip_core_pir_p9; dc->desc =3D "PowerNV Chip POWER9"; } =20 diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 2c225c928974..c676f800e28e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -56,6 +56,8 @@ typedef struct PnvChipClass { PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; + + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; =20 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" --=20 2.7.4