From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54357) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1brZH3-0002Uy-Jo for qemu-devel@nongnu.org; Tue, 04 Oct 2016 19:37:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1brZH2-0007Dt-Eb for qemu-devel@nongnu.org; Tue, 04 Oct 2016 19:37:25 -0400 Message-ID: <1475624216.5030.8.camel@aj.id.au> From: Andrew Jeffery Date: Wed, 05 Oct 2016 10:06:56 +1030 In-Reply-To: <1474977462-28032-6-git-send-email-clg@kaod.org> References: <1474977462-28032-1-git-send-email-clg@kaod.org> <1474977462-28032-6-git-send-email-clg@kaod.org> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-xqqjFhBvZx9jNWasP4uN" Mime-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 5/6] aspeed: create mapping regions for the maximum number of slaves List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-1?Q?C=E9dric?= Le Goater , Peter Maydell , Peter Crosthwaite Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org --=-xqqjFhBvZx9jNWasP4uN Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2016-09-27 at 13:57 +0200, C=C3=A9dric Le Goater wrote: > The SMC controller on the Aspeed SoC has a set of registers to > configure the mapping of each flash module in the SoC address > space. These mapping windows are configurable even though no SPI slave > is attached to the controller. >=20 > Also rewrite a bit the comments in the code on this topic. >=20 > Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery > --- > =C2=A0hw/ssi/aspeed_smc.c | 16 +++++++++++++--- > =C2=A01 file changed, 13 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c > index 21943f4e5dfa..ecf39ccfde0e 100644 > --- a/hw/ssi/aspeed_smc.c > +++ b/hw/ssi/aspeed_smc.c > @@ -417,12 +417,15 @@ static void aspeed_smc_realize(DeviceState *dev, Er= ror **errp) > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0aspeed_smc_reset(dev); > =C2=A0 > +=C2=A0=C2=A0=C2=A0=C2=A0/* The memory region for the controller register= s */ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0memory_region_init_io(&s->mmio, OBJECT(s), = &aspeed_smc_ops, s, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0s->ctrl->name, ASPEED_SMC_R_MAX * 4); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sysbus_init_mmio(sbd, &s->mmio); > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* Memory region where flash modules are re= mapped > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* The container memory region representing= the address space > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* window in which the flash modules are ma= pped. The size and > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* address depends on the SoC model and con= troller type. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0snprintf(name, sizeof(name), "%s.flash", s-= >ctrl->name); > =C2=A0 > @@ -431,9 +434,16 @@ static void aspeed_smc_realize(DeviceState *dev, Err= or **errp) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0s->ctrl->flash_window_size); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sysbus_init_mmio(sbd, &s->mmio_flash); > =C2=A0 > -=C2=A0=C2=A0=C2=A0=C2=A0s->flashes =3D g_new0(AspeedSMCFlash, s->num_cs)= ; > +=C2=A0=C2=A0=C2=A0=C2=A0s->flashes =3D g_new0(AspeedSMCFlash, s->ctrl->m= ax_slaves); > =C2=A0 > -=C2=A0=C2=A0=C2=A0=C2=A0for (i =3D 0; i < s->num_cs; ++i) { > +=C2=A0=C2=A0=C2=A0=C2=A0/* > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* Let's create a sub memory region for eac= h possible slave. All > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* have a configurable memory segment in th= e overall flash mapping > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* window of the controller but, there is n= ot necessarily a flash > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* module behind to handle the memory acces= ses. This depends on > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* the board configuration. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > +=C2=A0=C2=A0=C2=A0=C2=A0for (i =3D 0; i < s->ctrl->max_slaves; ++i) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0AspeedSMCFlash *fl = =3D &s->flashes[i]; > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0snprintf(name, size= of(name), "%s.%d", s->ctrl->name, i); --=-xqqjFhBvZx9jNWasP4uN Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJX9D0YAAoJEJ0dnzgO5LT5aDEQAJO8v0shV/NmmbBrYi7ZqKk9 B2I3KsCl6r6K4u+vzqU2y0zjxTGhSSFumDo3zXBCaPRPG7I93y2KgKcjVfpEOxKO jJRuwtB4okykDPhNi27Yd5aP5Je7cp1dFmxoxEXZEconTvxpVNUt2h91DA5b6z8p 9Tr1l0NR8quUC2llfj+ia1b3qWrKsE22qS+PKYWhkhfQ53rUgETYecc2pQcbd8hm wNP2CPhinQOPsE57mFpgtw8BFtIWCswsrv6sI8QmNoemz02lM+czkobRFNf+W1gJ W8kHRJSc+q5NblQpW/auzna3+/u2YCYz+mLmDA8+00wbzsyPwV7w5awGfmQ6xc7P KEJTmgHmRb2KivTnjrZMYF1btzaLpIZ/HWv1Dr4tb9Y7cefETbxQdH+pMOxDKY8f pQf5z6YWDxeV0dcqUt9XZDTUbrutTQ8K1Bsu44I7ShxReBrypzLKKFCuV4bIqdqa ReAge1RGhLcSG1ys6fTCX4ydflTOCKKvokeMAkCmqgKLDs41oed2i1dlwHxKkRCK UsPLRh9ZjPiHbhnK78AxsZOTUfCCQLXDGm/wDv3rrgwI5TqewI4yLCAgqTGrycmY WZYEmoSyQbTbhk30lXLVzQ8yrQTlLyi09j4aiqMYPuTOWbYb/vVN7bsKpnxfx0MI aMfw1K7zjDjHX9HShN0Y =lSbr -----END PGP SIGNATURE----- --=-xqqjFhBvZx9jNWasP4uN--