From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bs8c9-0004nX-Ck for qemu-devel@nongnu.org; Thu, 06 Oct 2016 09:21:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bs8c3-0006Xy-M8 for qemu-devel@nongnu.org; Thu, 06 Oct 2016 09:21:32 -0400 From: Peter Maydell Date: Thu, 6 Oct 2016 14:21:05 +0100 Message-Id: <1475760067-25756-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> References: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" MDCCINT_EL1 is part of the DCC debugger communication channel between the CPU and an attached external debugger. QEMU doesn't implement this, but since Linux may try to access this register we need to provide at least a dummy implementation. Signed-off-by: Peter Maydell --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 25f612d..23792ab 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_RW, .accessfn = access_tda, .type = ARM_CP_NOP }, + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications + * Channel but Linux may try to access this register. The 32-bit + * alias is DBGDCCINT. + */ + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, + .access = PL1_RW, .accessfn = access_tda, + .type = ARM_CP_NOP }, REGINFO_SENTINEL }; -- 2.7.4