From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsYTO-0003ng-DB for qemu-devel@nongnu.org; Fri, 07 Oct 2016 12:58:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bsYTM-0007tz-B0 for qemu-devel@nongnu.org; Fri, 07 Oct 2016 12:58:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37130) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsYTM-0007tp-1I for qemu-devel@nongnu.org; Fri, 07 Oct 2016 12:58:12 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7345CC0921B6 for ; Fri, 7 Oct 2016 16:58:11 +0000 (UTC) From: Paolo Bonzini Date: Fri, 7 Oct 2016 18:57:27 +0200 Message-Id: <1475859483-32234-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1475859483-32234-1-git-send-email-pbonzini@redhat.com> References: <1475859483-32234-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 03/39] hw/misc/edu: support MSI interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Xu From: Peter Xu So now edu device can support both line or msi interrupt, depending on how user configures it. Signed-off-by: Peter Xu Message-Id: <1475067819-21413-1-git-send-email-peterx@redhat.com> Signed-off-by: Paolo Bonzini --- docs/specs/edu.txt | 7 ++++++- hw/misc/edu.c | 18 ++++++++++++++++-- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/docs/specs/edu.txt b/docs/specs/edu.txt index 7f81467..0876310 100644 --- a/docs/specs/edu.txt +++ b/docs/specs/edu.txt @@ -52,7 +52,7 @@ size == 8 for the rest. 0x20 (RW) : status register, bitwise OR 0x01 -- computing factorial (RO) - 0x80 -- raise interrupt 0x01 after finishing factorial computation + 0x80 -- raise interrupt after finishing factorial computation 0x24 (RO) : interrupt status register It contains values which raised the interrupt (see interrupt raise @@ -87,6 +87,11 @@ An IRQ is generated when written to the interrupt raise register. The value appears in interrupt status register when the interrupt is raised and has to be written to the interrupt acknowledge register to lower it. +The device supports both INTx and MSI interrupt. By default, INTx is +used. Even if the driver disabled INTx and only uses MSI, it still +needs to update the acknowledge register at the end of the IRQ handler +routine. + DMA controller -------------- One has to specify, source, destination, size, and start the transfer. One diff --git a/hw/misc/edu.c b/hw/misc/edu.c index 888ba49..401039c 100644 --- a/hw/misc/edu.c +++ b/hw/misc/edu.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "hw/pci/pci.h" +#include "hw/pci/msi.h" #include "qemu/timer.h" #include "qemu/main-loop.h" /* iothread mutex */ #include "qapi/visitor.h" @@ -69,11 +70,20 @@ typedef struct { uint64_t dma_mask; } EduState; +static bool edu_msi_enabled(EduState *edu) +{ + return msi_enabled(&edu->pdev); +} + static void edu_raise_irq(EduState *edu, uint32_t val) { edu->irq_status |= val; if (edu->irq_status) { - pci_set_irq(&edu->pdev, 1); + if (edu_msi_enabled(edu)) { + msi_notify(&edu->pdev, 0); + } else { + pci_set_irq(&edu->pdev, 1); + } } } @@ -81,7 +91,7 @@ static void edu_lower_irq(EduState *edu, uint32_t val) { edu->irq_status &= ~val; - if (!edu->irq_status) { + if (!edu->irq_status && !edu_msi_enabled(edu)) { pci_set_irq(&edu->pdev, 0); } } @@ -342,6 +352,10 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp) pci_config_set_interrupt_pin(pci_conf, 1); + if (msi_init(pdev, 0, 1, true, false, errp)) { + return; + } + memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, "edu-mmio", 1 << 20); pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); -- 2.7.4