From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH v5 09/35] cputlb: Move probe_write out of softmmu_template.h
Date: Sun, 9 Oct 2016 18:41:40 -0500 [thread overview]
Message-ID: <1476056526-30740-10-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1476056526-30740-1-git-send-email-rth@twiddle.net>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
cputlb.c | 21 +++++++++++++++++++++
softmmu_template.h | 23 -----------------------
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 5575b73..0c9b77b 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -527,6 +527,27 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \
(ADDR) & TARGET_PAGE_MASK)
+/* Probe for whether the specified guest write access is permitted.
+ * If it is not permitted then an exception will be taken in the same
+ * way as if this were a real write access (and we will not return).
+ * Otherwise the function will return, and there will be a valid
+ * entry in the TLB for this access.
+ */
+void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
+ uintptr_t retaddr)
+{
+ int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+
+ if ((addr & TARGET_PAGE_MASK)
+ != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
+ /* TLB entry is for a different page */
+ if (!VICTIM_TLB_HIT(addr_write, addr)) {
+ tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ }
+ }
+}
+
#define MMUSUFFIX _mmu
#define DATA_SIZE 1
diff --git a/softmmu_template.h b/softmmu_template.h
index f9c51fe..538cff5 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -464,29 +464,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
}
#endif /* DATA_SIZE > 1 */
-
-#if DATA_SIZE == 1
-/* Probe for whether the specified guest write access is permitted.
- * If it is not permitted then an exception will be taken in the same
- * way as if this were a real write access (and we will not return).
- * Otherwise the function will return, and there will be a valid
- * entry in the TLB for this access.
- */
-void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
- uintptr_t retaddr)
-{
- int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
-
- if ((addr & TARGET_PAGE_MASK)
- != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
- /* TLB entry is for a different page */
- if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
- }
- }
-}
-#endif
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
#undef READ_ACCESS_TYPE
--
2.7.4
next prev parent reply other threads:[~2016-10-09 23:42 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-09 23:41 [Qemu-devel] [PATCH v5 00/35] cmpxchg-based emulation of atomics Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 01/35] atomics: add atomic_xor Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 02/35] atomics: add atomic_op_fetch variants Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 03/35] exec: Avoid direct references to Int128 parts Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 04/35] int128: Use __int128 if available Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 05/35] int128: Add int128_make128 Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 07/35] linux-user: enable parallel code generation on clone Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 08/35] cputlb: Replace SHIFT with DATA_SIZE Richard Henderson
2016-10-09 23:41 ` Richard Henderson [this message]
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 10/35] cputlb: Remove includes from softmmu_template.h Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 11/35] cputlb: Move most of iotlb code out of line Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 12/35] cputlb: Tidy some macros Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 13/35] tcg: Add atomic helpers Richard Henderson
2016-10-11 6:47 ` Alex Bennée
2016-10-11 12:00 ` Alex Bennée
2016-10-11 13:48 ` Richard Henderson
2016-10-11 15:21 ` Alex Bennée
2016-10-11 15:39 ` Richard Henderson
2016-10-11 15:55 ` Alex Bennée
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 14/35] tcg: Add atomic128 helpers Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 15/35] tcg: Add CONFIG_ATOMIC64 Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 16/35] tcg: Emit barriers with parallel_cpus Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 17/35] target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 18/35] target-i386: emulate LOCK'ed OP instructions using atomic helpers Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 19/35] target-i386: emulate LOCK'ed INC using atomic helper Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 20/35] target-i386: emulate LOCK'ed NOT " Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 21/35] target-i386: emulate LOCK'ed NEG using cmpxchg helper Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 22/35] target-i386: emulate LOCK'ed XADD using atomic helper Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 23/35] target-i386: emulate LOCK'ed BTX ops using atomic helpers Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 24/35] target-i386: emulate XCHG using atomic helper Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 25/35] target-i386: remove helper_lock() Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 26/35] tests: add atomic_add-bench Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 27/35] target-arm: Rearrange aa32 load and store functions Richard Henderson
2016-10-09 23:41 ` [Qemu-devel] [PATCH v5 28/35] target-arm: emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 29/35] target-arm: emulate SWP with atomic_xchg helper Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 31/35] linux-user: remove handling of ARM's EXCP_STREX Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 32/35] linux-user: remove handling of aarch64's EXCP_STREX Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 33/35] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 34/35] target-alpha: Introduce MMU_PHYS_IDX Richard Henderson
2016-10-09 23:42 ` [Qemu-devel] [PATCH v5 35/35] target-alpha: Emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-10 14:27 ` [Qemu-devel] [PATCH v5 06/35][RESEND] tcg: Add EXCP_ATOMIC Richard Henderson
2016-10-10 15:52 ` Alex Bennée
[not found] ` <1476056526-30740-7-git-send-email-rth@twiddle.net>
2016-10-10 16:17 ` [Qemu-devel] [PATCH v5 06/35] " Alex Bennée
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