From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btQnI-0003Z3-49 for qemu-devel@nongnu.org; Sun, 09 Oct 2016 22:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1btQnF-0003l1-AL for qemu-devel@nongnu.org; Sun, 09 Oct 2016 22:58:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37652) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btQnF-0003kZ-4z for qemu-devel@nongnu.org; Sun, 09 Oct 2016 22:58:21 -0400 Date: Mon, 10 Oct 2016 05:58:19 +0300 From: "Michael S. Tsirkin" Message-ID: <1476057841-21108-34-git-send-email-mst@redhat.com> References: <1476057841-21108-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1476057841-21108-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 33/33] intel-iommu: Check IOAPIC's Trigger Mode against the one in IRTE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Feng Wu , Peter Xu , Paolo Bonzini , Richard Henderson , Eduardo Habkost From: Feng Wu The Trigger Mode field of IOAPIC must match the Trigger Mode in the IRTE according to VT-d Spec 5.1.5.1. Signed-off-by: Feng Wu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9f4e64a..2efd69b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -27,6 +27,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/i386/pc.h" +#include "hw/i386/apic-msidef.h" #include "hw/boards.h" #include "hw/i386/x86-iommu.h" #include "hw/pci-host/q35.h" @@ -2209,6 +2210,8 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, } } else { uint8_t vector = origin->data & 0xff; + uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; + VTD_DPRINTF(IR, "received IOAPIC interrupt"); /* IOAPIC entry vector should be aligned with IRTE vector * (see vt-d spec 5.1.5.1). */ @@ -2217,6 +2220,15 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, "entry: %d, IRTE: %d, index: %d", vector, irq.vector, index); } + + /* The Trigger Mode field must match the Trigger Mode in the IRTE. + * (see vt-d spec 5.1.5.1). */ + if (trigger_mode != irq.trigger_mode) { + VTD_DPRINTF(GENERAL, "IOAPIC trigger mode inconsistent: " + "entry: %u, IRTE: %u, index: %d", + trigger_mode, irq.trigger_mode, index); + } + } /* -- MST