From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [Qemu-devel] [PATCH 08/16] target-sparc: Implement cas_asi/casx_asi inline
Date: Mon, 10 Oct 2016 10:17:00 -0500 [thread overview]
Message-ID: <1476112628-12241-9-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1476112628-12241-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/helper.h | 4 ---
target-sparc/ldst_helper.c | 29 -------------------
target-sparc/translate.c | 70 +++++++++++++++++++++++++++++++---------------
3 files changed, 47 insertions(+), 56 deletions(-)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index caa2a89..435c65e 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -18,7 +18,6 @@ DEF_HELPER_2(wrcwp, void, env, tl)
DEF_HELPER_FLAGS_2(array8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(popc, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(ldda_asi, TCG_CALL_NO_WG, void, env, tl, int)
-DEF_HELPER_FLAGS_5(casx_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
DEF_HELPER_FLAGS_2(set_softint, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_FLAGS_2(clear_softint, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_FLAGS_2(write_softint, TCG_CALL_NO_RWG, void, env, i64)
@@ -26,9 +25,6 @@ DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void, ptr, i64)
DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int)
DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
#endif
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-DEF_HELPER_FLAGS_5(cas_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
-#endif
DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 667b962..d90748e 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2150,37 +2150,8 @@ void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi)
QT0.high = h;
QT0.low = l;
}
-
-target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
- target_ulong val1, target_ulong val2,
- uint32_t asi)
-{
- target_ulong ret;
-
- ret = helper_ld_asi(env, addr, asi, MO_Q);
- if (val2 == ret) {
- helper_st_asi(env, addr, val1, asi, MO_Q);
- }
- return ret;
-}
#endif /* TARGET_SPARC64 */
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
- target_ulong val1, target_ulong val2, uint32_t asi)
-{
- target_ulong ret;
-
- val2 &= 0xffffffffUL;
- ret = helper_ld_asi(env, addr, asi, MO_UL);
- ret &= 0xffffffffUL;
- if (val2 == ret) {
- helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, MO_UL);
- }
- return ret;
-}
-#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
-
void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
{
/* XXX add 128 bit load */
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8d879a9..0fb361a 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2338,24 +2338,37 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
}
}
-static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
+static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpr,
int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEUL);
- TCGv val1, dst;
- TCGv_i32 r_asi;
+ TCGv cmpv, oldv, tmpv;
- if (da.type == GET_ASI_EXCP) {
+ switch (da.type) {
+ case GET_ASI_EXCP:
return;
+ case GET_ASI_DIRECT:
+ cmpv = tcg_temp_new();
+ oldv = tcg_temp_new();
+ tmpv = tcg_temp_new();
+ tcg_gen_ext32u_tl(cmpv, cmpr);
+
+ /* ??? Should be atomic. */
+ tcg_gen_qemu_ld_tl(oldv, addr, da.mem_idx, da.memop);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tmpv, oldv, cmpv,
+ gen_load_gpr(dc, rd), oldv);
+ tcg_gen_qemu_st_tl(tmpv, addr, da.mem_idx, da.memop);
+
+ gen_store_gpr(dc, rd, oldv);
+ tcg_temp_free(cmpv);
+ tcg_temp_free(oldv);
+ tcg_temp_free(tmpv);
+ break;
+ default:
+ /* ??? Should be DAE_invalid_asi. */
+ gen_exception(dc, TT_DATA_ACCESS);
+ break;
}
-
- save_state(dc);
- val1 = gen_load_gpr(dc, rd);
- dst = gen_dest_gpr(dc, rd);
- r_asi = tcg_const_i32(da.asi);
- gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
- tcg_temp_free_i32(r_asi);
- gen_store_gpr(dc, rd, dst);
}
static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
@@ -2668,23 +2681,34 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
}
}
-static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
+static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEQ);
- TCGv val1 = gen_load_gpr(dc, rd);
- TCGv dst = gen_dest_gpr(dc, rd);
- TCGv_i32 r_asi;
+ TCGv oldv, tmpv;
- if (da.type == GET_ASI_EXCP) {
+ switch (da.type) {
+ case GET_ASI_EXCP:
return;
+ case GET_ASI_DIRECT:
+ oldv = tcg_temp_new();
+ tmpv = tcg_temp_new();
+
+ /* ??? Should be atomic. */
+ tcg_gen_qemu_ld_tl(oldv, addr, da.mem_idx, da.memop);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tmpv, oldv, cmpv,
+ gen_load_gpr(dc, rd), oldv);
+ tcg_gen_qemu_st_tl(tmpv, addr, da.mem_idx, da.memop);
+
+ gen_store_gpr(dc, rd, oldv);
+ tcg_temp_free(oldv);
+ tcg_temp_free(tmpv);
+ break;
+ default:
+ /* ??? Should be DAE_invalid_asi. */
+ gen_exception(dc, TT_DATA_ACCESS);
+ break;
}
-
- save_state(dc);
- r_asi = tcg_const_i32(da.asi);
- gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
- tcg_temp_free_i32(r_asi);
- gen_store_gpr(dc, rd, dst);
}
#elif !defined(CONFIG_USER_ONLY)
--
2.7.4
next prev parent reply other threads:[~2016-10-10 15:17 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-10 15:16 [Qemu-devel] [PATCH 00/16] target-sparc improvements Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 01/16] target-sparc: Use overalignment flags for twinx and block asis Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 02/16] target-sparc: Introduce cpu_raise_exception_ra Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 03/16] target-sparc: Add MMU_PHYS_IDX Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 04/16] target-sparc: Use MMU_PHYS_IDX for bypass asis Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 05/16] target-sparc: Handle more twinx asis Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 06/16] target-sparc: Implement swap_asi inline Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 07/16] target-sparc: Implement ldstub_asi inline Richard Henderson
2016-10-10 15:17 ` Richard Henderson [this message]
2016-10-10 15:17 ` [Qemu-devel] [PATCH 09/16] target-sparc: Implement BCOPY/BFILL inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 10/16] target-sparc: Remove asi helper code handled inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 11/16] target-sparc: Implement ldqf and stqf inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 12/16] target-sparc: Allow 4-byte alignment on fp mem ops Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 13/16] target-sparc: Remove MMU_MODE*_SUFFIX Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 14/16] target-sparc: Optmize writeback of cpu_cond Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 15/16] target-sparc: Use tcg_gen_atomic_xchg_tl Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 16/16] target-sparc: Use tcg_gen_atomic_cmpxchg_tl Richard Henderson
2016-10-10 17:02 ` [Qemu-devel] [PATCH 00/16] target-sparc improvements no-reply
2016-10-11 21:42 ` Mark Cave-Ayland
2016-10-12 1:42 ` Richard Henderson
2016-10-15 8:08 ` Mark Cave-Ayland
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