From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buBBC-00028k-61 for qemu-devel@nongnu.org; Wed, 12 Oct 2016 00:30:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buBBA-0003Z2-6J for qemu-devel@nongnu.org; Wed, 12 Oct 2016 00:30:09 -0400 From: David Gibson Date: Wed, 12 Oct 2016 15:29:50 +1100 Message-Id: <1476246592-24228-6-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1476246592-24228-1-git-send-email-david@gibson.dropbear.id.au> References: <1476246592-24228-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PATCH 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: lvivier@redhat.com, agraf@suse.de Cc: mst@redhat.com, abolonga@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, mdroth@linux.vnet.ibm.com, benh@kernel.crashing.org, David Gibson Currently the default PCI host bridge for the 'pseries' machine type is constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in guest memory space. This means that if > 1TiB of guest RAM is specified, the RAM will collide with the PCI IO windows, causing serious problems. Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because there's a little unused space at the bottom of the area reserved for PCI, but essentially this means that > 1TiB of RAM has never worked with the pseries machine type. This patch fixes this by altering the placement of PHBs on large-RAM VMs. Instead of always placing the first PHB at 1TiB, it is placed at the next 1 TiB boundary after the maximum RAM address. Technically, this changes behaviour in a migration-breaking way for existing machines with > 1TiB maximum memory, but since having > 1 TiB memory was broken anyway, this seems like a reasonable trade-off. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f6e9c2a..08a8327 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2376,15 +2376,25 @@ static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, unsigned n_dma, uint32_t *liobns, Error **errp) { const uint64_t base_buid = 0x800000020000000ULL; - const hwaddr phb0_base = 0x10000000000ULL; /* 1 TiB */ const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ const hwaddr pio_offset = 0x80000000; /* 2 GiB */ const uint32_t max_index = 255; + const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ - hwaddr phb_base; + uint64_t ram_top = MACHINE(spapr)->ram_size; + hwaddr phb0_base, phb_base; int i; + if (MACHINE(spapr)->maxram_size > ram_top) { + ram_top = spapr->hotplug_memory.base + + memory_region_size(&spapr->hotplug_memory.mr); + } + + phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); + + fprintf(stderr, "DEBUG: ram_top = 0x%016"PRIx64" phb0 @ 0x%016"HWADDR_PRIX"\n", + ram_top, phb0_base); if (index > max_index) { error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", max_index); -- 2.7.4