From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38690) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bwCqJ-0001JQ-62 for qemu-devel@nongnu.org; Mon, 17 Oct 2016 14:41:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bwCqH-0001Bi-IW for qemu-devel@nongnu.org; Mon, 17 Oct 2016 14:40:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47361) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bwCqH-00018D-AU for qemu-devel@nongnu.org; Mon, 17 Oct 2016 14:40:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bwCqG-00058H-IW for qemu-devel@nongnu.org; Mon, 17 Oct 2016 19:40:56 +0100 From: Peter Maydell Date: Mon, 17 Oct 2016 19:40:39 +0100 Message-Id: <1476729644-4595-21-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1476729644-4595-1-git-send-email-peter.maydell@linaro.org> References: <1476729644-4595-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 20/25] target-arm: Comments added to identify cases in a switch List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Thomas Hanson 3 cases in a switch in disas_exc() require reference to the ARM ARM spec in order to determine what case they're handling. Signed-off-by: Thomas Hanson Message-id: 1476301853-15774-5-git-send-email-thomas.hanson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 16716a2..96c2227 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1667,12 +1667,12 @@ static void disas_exc(DisasContext *s, uint32_t insn) * instruction works properly. */ switch (op2_ll) { - case 1: + case 1: /* SVC */ gen_ss_advance(s); gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), default_exception_el(s)); break; - case 2: + case 2: /* HVC */ if (s->current_el == 0) { unallocated_encoding(s); break; @@ -1685,7 +1685,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_ss_advance(s); gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; - case 3: + case 3: /* SMC */ if (s->current_el == 0) { unallocated_encoding(s); break; -- 2.7.4