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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 11/35] cputlb: Move most of iotlb code out of line
Date: Sat, 22 Oct 2016 14:05:00 -0700	[thread overview]
Message-ID: <1477170324-17783-12-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1477170324-17783-1-git-send-email-rth@twiddle.net>

Saves 2k code size off of a cold path.

Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cputlb.c           | 37 +++++++++++++++++++++++++++++++++++++
 softmmu_template.h | 52 ++++++++++------------------------------------------
 2 files changed, 47 insertions(+), 42 deletions(-)

diff --git a/cputlb.c b/cputlb.c
index 0c9b77b..1bee47d 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -498,6 +498,43 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
     return qemu_ram_addr_from_host_nofail(p);
 }
 
+static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
+                         target_ulong addr, uintptr_t retaddr, int size)
+{
+    CPUState *cpu = ENV_GET_CPU(env);
+    hwaddr physaddr = iotlbentry->addr;
+    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
+    uint64_t val;
+
+    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
+    cpu->mem_io_pc = retaddr;
+    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
+        cpu_io_recompile(cpu, retaddr);
+    }
+
+    cpu->mem_io_vaddr = addr;
+    memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs);
+    return val;
+}
+
+static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
+                      uint64_t val, target_ulong addr,
+                      uintptr_t retaddr, int size)
+{
+    CPUState *cpu = ENV_GET_CPU(env);
+    hwaddr physaddr = iotlbentry->addr;
+    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
+
+    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
+    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
+        cpu_io_recompile(cpu, retaddr);
+    }
+
+    cpu->mem_io_vaddr = addr;
+    cpu->mem_io_pc = retaddr;
+    memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs);
+}
+
 /* Return true if ADDR is present in the victim tlb, and has been copied
    back to the main tlb.  */
 static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
diff --git a/softmmu_template.h b/softmmu_template.h
index b9532a4..035ffc8 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -112,25 +112,12 @@
 
 #ifndef SOFTMMU_CODE_ACCESS
 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
-                                              CPUIOTLBEntry *iotlbentry,
+                                              size_t mmu_idx, size_t index,
                                               target_ulong addr,
                                               uintptr_t retaddr)
 {
-    uint64_t val;
-    CPUState *cpu = ENV_GET_CPU(env);
-    hwaddr physaddr = iotlbentry->addr;
-    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
-
-    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
-    cpu->mem_io_pc = retaddr;
-    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
-        cpu_io_recompile(cpu, retaddr);
-    }
-
-    cpu->mem_io_vaddr = addr;
-    memory_region_dispatch_read(mr, physaddr, &val, DATA_SIZE,
-                                iotlbentry->attrs);
-    return val;
+    CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+    return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);
 }
 #endif
 
@@ -161,15 +148,13 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
 
     /* Handle an IO access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
         if ((addr & (DATA_SIZE - 1)) != 0) {
             goto do_unaligned_access;
         }
-        iotlbentry = &env->iotlb[mmu_idx][index];
 
         /* ??? Note that the io helpers always read data in the target
            byte ordering.  We should push the LE/BE request down into io.  */
-        res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
+        res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
         res = TGT_LE(res);
         return res;
     }
@@ -230,15 +215,13 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
 
     /* Handle an IO access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
         if ((addr & (DATA_SIZE - 1)) != 0) {
             goto do_unaligned_access;
         }
-        iotlbentry = &env->iotlb[mmu_idx][index];
 
         /* ??? Note that the io helpers always read data in the target
            byte ordering.  We should push the LE/BE request down into io.  */
-        res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
+        res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
         res = TGT_BE(res);
         return res;
     }
@@ -289,24 +272,13 @@ WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
 #endif
 
 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
-                                          CPUIOTLBEntry *iotlbentry,
+                                          size_t mmu_idx, size_t index,
                                           DATA_TYPE val,
                                           target_ulong addr,
                                           uintptr_t retaddr)
 {
-    CPUState *cpu = ENV_GET_CPU(env);
-    hwaddr physaddr = iotlbentry->addr;
-    MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
-
-    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
-    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
-        cpu_io_recompile(cpu, retaddr);
-    }
-
-    cpu->mem_io_vaddr = addr;
-    cpu->mem_io_pc = retaddr;
-    memory_region_dispatch_write(mr, physaddr, val, DATA_SIZE,
-                                 iotlbentry->attrs);
+    CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+    return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);
 }
 
 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
@@ -334,16 +306,14 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 
     /* Handle an IO access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
         if ((addr & (DATA_SIZE - 1)) != 0) {
             goto do_unaligned_access;
         }
-        iotlbentry = &env->iotlb[mmu_idx][index];
 
         /* ??? Note that the io helpers always read data in the target
            byte ordering.  We should push the LE/BE request down into io.  */
         val = TGT_LE(val);
-        glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+        glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
         return;
     }
 
@@ -412,16 +382,14 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 
     /* Handle an IO access.  */
     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
-        CPUIOTLBEntry *iotlbentry;
         if ((addr & (DATA_SIZE - 1)) != 0) {
             goto do_unaligned_access;
         }
-        iotlbentry = &env->iotlb[mmu_idx][index];
 
         /* ??? Note that the io helpers always read data in the target
            byte ordering.  We should push the LE/BE request down into io.  */
         val = TGT_BE(val);
-        glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+        glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
         return;
     }
 
-- 
2.7.4

  parent reply	other threads:[~2016-10-22 21:05 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-22 21:04 [Qemu-devel] [PULL 00/35] cmpxchg atomic operations Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 01/35] atomics: add atomic_xor Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 02/35] atomics: add atomic_op_fetch variants Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 03/35] exec: Avoid direct references to Int128 parts Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 04/35] int128: Use __int128 if available Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 05/35] int128: Add int128_make128 Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 07/35] linux-user: enable parallel code generation on clone Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 08/35] cputlb: Replace SHIFT with DATA_SIZE Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 09/35] cputlb: Move probe_write out of softmmu_template.h Richard Henderson
2016-10-22 21:04 ` [Qemu-devel] [PULL 10/35] cputlb: Remove includes from softmmu_template.h Richard Henderson
2016-10-22 21:05 ` Richard Henderson [this message]
2016-10-22 21:05 ` [Qemu-devel] [PULL 12/35] cputlb: Tidy some macros Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 13/35] tcg: Add atomic helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 14/35] tcg: Add atomic128 helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 15/35] tcg: Add CONFIG_ATOMIC64 Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 16/35] tcg: Emit barriers with parallel_cpus Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 17/35] target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 18/35] target-i386: emulate LOCK'ed OP instructions using atomic helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 19/35] target-i386: emulate LOCK'ed INC using atomic helper Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 20/35] target-i386: emulate LOCK'ed NOT " Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 21/35] target-i386: emulate LOCK'ed NEG using cmpxchg helper Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 22/35] target-i386: emulate LOCK'ed XADD using atomic helper Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 23/35] target-i386: emulate LOCK'ed BTX ops using atomic helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 24/35] target-i386: emulate XCHG using atomic helper Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 25/35] target-i386: remove helper_lock() Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 26/35] tests: add atomic_add-bench Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 27/35] target-arm: Rearrange aa32 load and store functions Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 28/35] target-arm: emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 29/35] target-arm: emulate SWP with atomic_xchg helper Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 31/35] linux-user: remove handling of ARM's EXCP_STREX Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 32/35] linux-user: remove handling of aarch64's EXCP_STREX Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 33/35] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 34/35] target-alpha: Introduce MMU_PHYS_IDX Richard Henderson
2016-10-22 21:05 ` [Qemu-devel] [PULL 35/35] target-alpha: Emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-24 10:51 ` [Qemu-devel] [PULL 00/35] cmpxchg atomic operations Peter Maydell
2016-10-24 12:37   ` Paolo Bonzini
2016-10-24 14:02     ` Peter Maydell
2016-10-24 17:27   ` Richard Henderson
2016-10-24 18:02     ` Peter Maydell

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