From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byjEJ-0002c5-95 for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:40:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byjEI-0005YQ-FZ for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:40:11 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:36070) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1byjEI-0005Wi-79 for qemu-devel@nongnu.org; Mon, 24 Oct 2016 13:40:10 -0400 Received: by mail-pf0-x241.google.com with SMTP id r16so17097613pfg.3 for ; Mon, 24 Oct 2016 10:40:10 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 24 Oct 2016 10:39:35 -0700 Message-Id: <1477330788-14996-25-git-send-email-rth@twiddle.net> In-Reply-To: <1477330788-14996-1-git-send-email-rth@twiddle.net> References: <1477330788-14996-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v8 24/37] target-i386: emulate LOCK'ed XADD using atomic helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org From: "Emilio G. Cota" [rth: Move load of reg value to common location.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-17-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index d2edbd9..3e6011b 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -5134,19 +5134,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; + gen_op_mov_v_reg(ot, cpu_T0, reg); if (mod == 3) { rm = (modrm & 7) | REX_B(s); - gen_op_mov_v_reg(ot, cpu_T0, reg); gen_op_mov_v_reg(ot, cpu_T1, rm); tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1); gen_op_mov_reg_v(ot, reg, cpu_T1); gen_op_mov_reg_v(ot, rm, cpu_T0); } else { gen_lea_modrm(env, s, modrm); - gen_op_mov_v_reg(ot, cpu_T0, reg); - gen_op_ld_v(s, ot, cpu_T1, cpu_A0); - tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1); - gen_op_st_v(s, ot, cpu_T0, cpu_A0); + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_fetch_add_tl(cpu_T1, cpu_A0, cpu_T0, + s->mem_index, ot | MO_LE); + tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1); + } else { + gen_op_ld_v(s, ot, cpu_T1, cpu_A0); + tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1); + gen_op_st_v(s, ot, cpu_T0, cpu_A0); + } gen_op_mov_reg_v(ot, reg, cpu_T1); } gen_op_update2_cc(); -- 2.7.4