From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH v8 29/37] target-arm: Rearrange aa32 load and store functions
Date: Mon, 24 Oct 2016 10:39:40 -0700 [thread overview]
Message-ID: <1477330788-14996-30-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1477330788-14996-1-git-send-email-rth@twiddle.net>
Stop specializing on TARGET_LONG_BITS == 32; unconditionally allocate
a temp and expand with tcg_gen_extu_i32_tl. Split out gen_aa32_addr,
gen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate.c | 171 +++++++++++++++++++------------------------------
1 file changed, 66 insertions(+), 105 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 164b52a..b5c1b74 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -931,145 +931,106 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
* These functions work like tcg_gen_qemu_{ld,st}* except
* that the address argument is TCGv_i32 rather than TCGv.
*/
-#if TARGET_LONG_BITS == 32
-#define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
-static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 addr, int index) \
-{ \
- TCGMemOp opc = (OPC) | s->be_data; \
- /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
- if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
- TCGv addr_be = tcg_temp_new(); \
- tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
- tcg_gen_qemu_ld_i32(val, addr_be, index, opc); \
- tcg_temp_free(addr_be); \
- return; \
- } \
- tcg_gen_qemu_ld_i32(val, addr, index, opc); \
-}
-
-#define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
-static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 addr, int index) \
-{ \
- TCGMemOp opc = (OPC) | s->be_data; \
- /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
- if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
- TCGv addr_be = tcg_temp_new(); \
- tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
- tcg_gen_qemu_st_i32(val, addr_be, index, opc); \
- tcg_temp_free(addr_be); \
- return; \
- } \
- tcg_gen_qemu_st_i32(val, addr, index, opc); \
-}
-
-static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 addr, int index)
+static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
{
- TCGMemOp opc = MO_Q | s->be_data;
- tcg_gen_qemu_ld_i64(val, addr, index, opc);
+ TCGv addr = tcg_temp_new();
+ tcg_gen_extu_i32_tl(addr, a32);
+
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
- tcg_gen_rotri_i64(val, val, 32);
+ if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {
+ tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));
}
+ return addr;
}
-static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 addr, int index)
+static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, TCGMemOp opc)
{
- TCGMemOp opc = MO_Q | s->be_data;
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
- TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_rotri_i64(tmp, val, 32);
- tcg_gen_qemu_st_i64(tmp, addr, index, opc);
- tcg_temp_free_i64(tmp);
- return;
- }
- tcg_gen_qemu_st_i64(val, addr, index, opc);
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+ tcg_gen_qemu_ld_i32(val, addr, index, opc);
+ tcg_temp_free(addr);
}
-#else
+static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, TCGMemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+ tcg_gen_qemu_st_i32(val, addr, index, opc);
+ tcg_temp_free(addr);
+}
-#define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
+#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 addr, int index) \
+ TCGv_i32 a32, int index) \
{ \
- TCGMemOp opc = (OPC) | s->be_data; \
- TCGv addr64 = tcg_temp_new(); \
- tcg_gen_extu_i32_i64(addr64, addr); \
- /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
- if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
- tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
- } \
- tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
- tcg_temp_free(addr64); \
-}
-
-#define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
+ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
+}
+
+#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 addr, int index) \
+ TCGv_i32 a32, int index) \
{ \
- TCGMemOp opc = (OPC) | s->be_data; \
- TCGv addr64 = tcg_temp_new(); \
- tcg_gen_extu_i32_i64(addr64, addr); \
- /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
- if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
- tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
- } \
- tcg_gen_qemu_st_i32(val, addr64, index, opc); \
- tcg_temp_free(addr64); \
+ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
}
-static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 addr, int index)
+static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
{
- TCGMemOp opc = MO_Q | s->be_data;
- TCGv addr64 = tcg_temp_new();
- tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_ld_i64(val, addr64, index, opc);
-
/* Not needed for user-mode BE32, where we use MO_BE instead. */
if (!IS_USER_ONLY && s->sctlr_b) {
tcg_gen_rotri_i64(val, val, 32);
}
- tcg_temp_free(addr64);
}
-static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 addr, int index)
+static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, TCGMemOp opc)
{
- TCGMemOp opc = MO_Q | s->be_data;
- TCGv addr64 = tcg_temp_new();
- tcg_gen_extu_i32_i64(addr64, addr);
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
+ gen_aa32_frob64(s, val);
+ tcg_temp_free(addr);
+}
+
+static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index)
+{
+ gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
+}
+
+static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, TCGMemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
if (!IS_USER_ONLY && s->sctlr_b) {
- TCGv tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_rotri_i64(tmp, val, 32);
- tcg_gen_qemu_st_i64(tmp, addr64, index, opc);
- tcg_temp_free(tmp);
+ tcg_gen_qemu_st_i64(tmp, addr, index, opc);
+ tcg_temp_free_i64(tmp);
} else {
- tcg_gen_qemu_st_i64(val, addr64, index, opc);
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
}
- tcg_temp_free(addr64);
+ tcg_temp_free(addr);
}
-#endif
+static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index)
+{
+ gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
+}
-DO_GEN_LD(8s, MO_SB, 3)
-DO_GEN_LD(8u, MO_UB, 3)
-DO_GEN_LD(16s, MO_SW, 2)
-DO_GEN_LD(16u, MO_UW, 2)
-DO_GEN_LD(32u, MO_UL, 0)
+DO_GEN_LD(8s, MO_SB)
+DO_GEN_LD(8u, MO_UB)
+DO_GEN_LD(16s, MO_SW)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
/* 'a' variants include an alignment check */
-DO_GEN_LD(16ua, MO_UW | MO_ALIGN, 2)
-DO_GEN_LD(32ua, MO_UL | MO_ALIGN, 0)
-DO_GEN_ST(8, MO_UB, 3)
-DO_GEN_ST(16, MO_UW, 2)
-DO_GEN_ST(32, MO_UL, 0)
+DO_GEN_LD(16ua, MO_UW | MO_ALIGN)
+DO_GEN_LD(32ua, MO_UL | MO_ALIGN)
+DO_GEN_ST(8, MO_UB)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
--
2.7.4
next prev parent reply other threads:[~2016-10-24 17:40 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-24 17:39 [Qemu-devel] [PATCH v8 00/37] cmpxchg atomic operations Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 01/37] atomics: Add parameters to macros Richard Henderson
2016-10-24 18:13 ` Emilio G. Cota
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 02/37] atomics: add atomic_xor Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 03/37] atomics: add atomic_op_fetch variants Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 04/37] atomics: Add __nocheck atomic operations Richard Henderson
2016-10-24 18:16 ` Emilio G. Cota
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 05/37] exec: Avoid direct references to Int128 parts Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 06/37] int128: Use __int128 if available Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 07/37] int128: Add int128_make128 Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 09/37] linux-user: enable parallel code generation on clone Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 10/37] cputlb: Replace SHIFT with DATA_SIZE Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 11/37] cputlb: Move probe_write out of softmmu_template.h Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 12/37] cputlb: Remove includes from softmmu_template.h Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 13/37] cputlb: Move most of iotlb code out of line Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 14/37] cputlb: Tidy some macros Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 15/37] tcg: Add atomic helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 16/37] tcg: Add atomic128 helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 17/37] tcg: Add CONFIG_ATOMIC64 Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 18/37] tcg: Emit barriers with parallel_cpus Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 19/37] target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 20/37] target-i386: emulate LOCK'ed OP instructions using atomic helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 21/37] target-i386: emulate LOCK'ed INC using atomic helper Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 22/37] target-i386: emulate LOCK'ed NOT " Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 23/37] target-i386: emulate LOCK'ed NEG using cmpxchg helper Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 24/37] target-i386: emulate LOCK'ed XADD using atomic helper Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 25/37] target-i386: emulate LOCK'ed BTX ops using atomic helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 26/37] target-i386: emulate XCHG using atomic helper Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 27/37] target-i386: remove helper_lock() Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 28/37] tests: add atomic_add-bench Richard Henderson
2016-10-24 17:39 ` Richard Henderson [this message]
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 30/37] target-arm: emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 31/37] target-arm: emulate SWP with atomic_xchg helper Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 32/37] target-arm: emulate aarch64's LL/SC using cmpxchg helpers Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 33/37] linux-user: remove handling of ARM's EXCP_STREX Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 34/37] linux-user: remove handling of aarch64's EXCP_STREX Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 35/37] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 36/37] target-alpha: Introduce MMU_PHYS_IDX Richard Henderson
2016-10-24 17:39 ` [Qemu-devel] [PATCH v8 37/37] target-alpha: Emulate LL/SC using cmpxchg helpers Richard Henderson
2016-10-24 18:27 ` [Qemu-devel] [PATCH v8 00/37] cmpxchg atomic operations Emilio G. Cota
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1477330788-14996-30-git-send-email-rth@twiddle.net \
--to=rth@twiddle.net \
--cc=alex.bennee@linaro.org \
--cc=cota@braap.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).