From: Guenter Roeck <linux@roeck-us.net>
To: qemu-devel@nongnu.org
Cc: Jean-Christophe Dubois <jcd@tribudubois.net>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
Guenter Roeck <linux@roeck-us.net>
Subject: [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write
Date: Mon, 24 Oct 2016 19:03:25 -0700 [thread overview]
Message-ID: <1477361005-18646-1-git-send-email-linux@roeck-us.net> (raw)
Writing the ISR register is supposed to clear interrupt status bits,
not to set them.
This patch makes '-M sabrelite' work without devicetree changes (Linux
kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
multi_v7_defconfig; mainline has different problems).
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
hw/gpio/imx_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index f3574aa..c36c394 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
break;
case ISR_ADDR:
- s->isr |= ~value;
+ s->isr &= ~value;
imx_gpio_set_all_int_lines(s);
break;
--
2.5.0
next reply other threads:[~2016-10-25 2:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-25 2:03 Guenter Roeck [this message]
2016-10-25 9:47 ` [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write Jean-Christophe DUBOIS
2016-10-25 11:11 ` Peter Maydell
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