* [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write
@ 2016-10-25 2:03 Guenter Roeck
2016-10-25 9:47 ` Jean-Christophe DUBOIS
2016-10-25 11:11 ` Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Guenter Roeck @ 2016-10-25 2:03 UTC (permalink / raw)
To: qemu-devel
Cc: Jean-Christophe Dubois, Peter Crosthwaite, Peter Maydell,
Guenter Roeck
Writing the ISR register is supposed to clear interrupt status bits,
not to set them.
This patch makes '-M sabrelite' work without devicetree changes (Linux
kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
multi_v7_defconfig; mainline has different problems).
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
hw/gpio/imx_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index f3574aa..c36c394 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
break;
case ISR_ADDR:
- s->isr |= ~value;
+ s->isr &= ~value;
imx_gpio_set_all_int_lines(s);
break;
--
2.5.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write
2016-10-25 2:03 [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write Guenter Roeck
@ 2016-10-25 9:47 ` Jean-Christophe DUBOIS
2016-10-25 11:11 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Jean-Christophe DUBOIS @ 2016-10-25 9:47 UTC (permalink / raw)
To: Guenter Roeck, qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite
Le 25/10/2016 à 04:03, Guenter Roeck a écrit :
> Writing the ISR register is supposed to clear interrupt status bits,
> not to set them.
>
> This patch makes '-M sabrelite' work without devicetree changes (Linux
> kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
> multi_v7_defconfig; mainline has different problems).
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> ---
> hw/gpio/imx_gpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
> index f3574aa..c36c394 100644
> --- a/hw/gpio/imx_gpio.c
> +++ b/hw/gpio/imx_gpio.c
> @@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
> break;
>
> case ISR_ADDR:
> - s->isr |= ~value;
> + s->isr &= ~value;
> imx_gpio_set_all_int_lines(s);
> break;
>
acked-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Thanks.
JC
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write
2016-10-25 2:03 [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write Guenter Roeck
2016-10-25 9:47 ` Jean-Christophe DUBOIS
@ 2016-10-25 11:11 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2016-10-25 11:11 UTC (permalink / raw)
To: Guenter Roeck; +Cc: QEMU Developers, Jean-Christophe Dubois, Peter Crosthwaite
On 25 October 2016 at 03:03, Guenter Roeck <linux@roeck-us.net> wrote:
> Writing the ISR register is supposed to clear interrupt status bits,
> not to set them.
>
> This patch makes '-M sabrelite' work without devicetree changes (Linux
> kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
> multi_v7_defconfig; mainline has different problems).
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> ---
> hw/gpio/imx_gpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
> index f3574aa..c36c394 100644
> --- a/hw/gpio/imx_gpio.c
> +++ b/hw/gpio/imx_gpio.c
> @@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
> break;
>
> case ISR_ADDR:
> - s->isr |= ~value;
> + s->isr &= ~value;
> imx_gpio_set_all_int_lines(s);
> break;
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-10-25 2:03 [Qemu-devel] [PATCH] i.MX: Fix GPIO ISR register write Guenter Roeck
2016-10-25 9:47 ` Jean-Christophe DUBOIS
2016-10-25 11:11 ` Peter Maydell
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