From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: schwab@linux-m68k.org, agraf@suse.de,
Richard Henderson <rth@twiddle.net>,
gerg@uclinux.org, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PULL 20/23] target-m68k: Introduce DisasCompare
Date: Tue, 25 Oct 2016 21:03:16 +0200 [thread overview]
Message-ID: <1477422199-11208-21-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1477422199-11208-1-git-send-email-laurent@vivier.eu>
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/translate.c | 85 +++++++++++++++++++++++++++++++++++--------------
1 file changed, 61 insertions(+), 24 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 85d5c95..4a650e1 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -759,8 +759,15 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
return NULL_QREG;
}
-/* This generates a conditional branch, clobbering all temporaries. */
-static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+typedef struct {
+ TCGCond tcond;
+ bool g1;
+ bool g2;
+ TCGv v1;
+ TCGv v2;
+} DisasCompare;
+
+static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv tmp, tmp2;
TCGCond tcond;
@@ -768,61 +775,92 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
- update_cc_op(s);
+
+ c->g1 = 1;
+ c->g2 = 0;
+ c->v2 = tcg_const_i32(0);
+
switch (cond) {
case 0: /* T */
- tcg_gen_br(l1);
- return;
case 1: /* F */
- return;
+ c->v1 = c->v2;
+ tcond = TCG_COND_NEVER;
+ break;
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
- tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
+ tcond = TCG_COND_NE;
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
- tmp = QREG_CC_C;
- tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
+ c->v1 = QREG_CC_C;
+ tcond = TCG_COND_NE;
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
- tmp = QREG_CC_Z;
- tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE);
+ c->v1 = QREG_CC_Z;
+ tcond = TCG_COND_EQ;
break;
case 8: /* VC (!V) */
case 9: /* VS (V) */
- tmp = QREG_CC_V;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_V;
+ tcond = TCG_COND_LT;
break;
case 10: /* PL (!N) */
case 11: /* MI (N) */
- tmp = QREG_CC_N;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_N;
+ tcond = TCG_COND_LT;
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
- tmp = tcg_temp_new();
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_neg_i32(tmp, tmp);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcg_temp_free(tmp2);
+ tcond = TCG_COND_LT;
break;
default:
/* Should ever happen. */
abort();
}
- tcg_gen_brcondi_i32(tcond, tmp, 0, l1);
+ if ((cond & 1) == 0) {
+ tcond = tcg_invert_cond(tcond);
+ }
+ c->tcond = tcond;
+}
+
+static void free_cond(DisasCompare *c)
+{
+ if (!c->g1) {
+ tcg_temp_free(c->v1);
+ }
+ if (!c->g2) {
+ tcg_temp_free(c->v2);
+ }
+}
+
+static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+{
+ DisasCompare c;
+
+ gen_cc_cond(&c, s, cond);
+ update_cc_op(s);
+ tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
+ free_cond(&c);
}
DISAS_INSN(scc)
@@ -1678,7 +1716,6 @@ DISAS_INSN(branch)
/* bsr */
gen_push(s, tcg_const_i32(s->pc));
}
- update_cc_op(s);
if (op > 1) {
/* Bcc */
l1 = gen_new_label();
--
2.7.4
next prev parent reply other threads:[~2016-10-25 19:04 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-25 19:02 [Qemu-devel] [PULL 00/23] M68k part1 patches Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 01/23] target-m68k: fix DEBUG_DISPATCH Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 02/23] target-m68k: Build the opcode table only once to avoid multithreading issues Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 03/23] target-m68k: define m680x0 CPUs and features Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 04/23] target-m68k: manage scaled index Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 05/23] target-m68k: introduce read_imXX() functions Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 06/23] target-m68k: set disassembler mode to 680x0 or coldfire Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 07/23] target-m68k: define operand sizes Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 08/23] target-m68k: set PAGE_BITS to 12 for m68k Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 09/23] target-m68k: REG() macro cleanup Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 10/23] target-m68k: allow to update flags with operation on words and bytes Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 11/23] target-m68k: Replace helper_xflag_lt with setcond Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 12/23] target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit() Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 13/23] target-m68k: update move to/from ccr/sr Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 14/23] target-m68k: don't update cc_dest in helpers Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 15/23] target-m68k: update CPU flags management Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 16/23] target-m68k: Print flags properly Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 17/23] target-m68k: Some fixes to SR and flags management Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 18/23] target-m68k: Remove incorrect clearing of cc_x Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 19/23] target-m68k: Reorg flags handling Laurent Vivier
2016-10-25 19:03 ` Laurent Vivier [this message]
2016-10-25 19:03 ` [Qemu-devel] [PULL 21/23] target-m68k: Use setcond for scc Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 22/23] target-m68k: Optimize some comparisons Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 23/23] target-m68k: Optimize gen_flush_flags Laurent Vivier
2016-10-27 11:45 ` [Qemu-devel] [PULL 00/23] M68k part1 patches Peter Maydell
2016-10-27 11:47 ` Laurent Vivier
2016-10-27 11:50 ` Peter Maydell
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