From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: schwab@linux-m68k.org, agraf@suse.de,
Richard Henderson <rth@twiddle.net>,
gerg@uclinux.org, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PULL 23/23] target-m68k: Optimize gen_flush_flags
Date: Tue, 25 Oct 2016 21:03:19 +0200 [thread overview]
Message-ID: <1477422199-11208-24-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1477422199-11208-1-git-send-email-laurent@vivier.eu>
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/translate.c | 56 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 52aa800..6c6173a 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -458,18 +458,66 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
static void gen_flush_flags(DisasContext *s)
{
- TCGv tmp;
+ TCGv t0, t1;
switch (s->cc_op) {
case CC_OP_FLAGS:
return;
+
+ case CC_OP_ADD:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for addition. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_SUB:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_CMP:
+ tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
+ tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
+ break;
+
+ case CC_OP_LOGIC:
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ break;
+
case CC_OP_DYNAMIC:
gen_helper_flush_flags(cpu_env, QREG_CC_OP);
break;
+
default:
- tmp = tcg_const_i32(s->cc_op);
- gen_helper_flush_flags(cpu_env, tmp);
- tcg_temp_free(tmp);
+ t0 = tcg_const_i32(s->cc_op);
+ gen_helper_flush_flags(cpu_env, t0);
+ tcg_temp_free(t0);
break;
}
--
2.7.4
next prev parent reply other threads:[~2016-10-25 19:04 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-25 19:02 [Qemu-devel] [PULL 00/23] M68k part1 patches Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 01/23] target-m68k: fix DEBUG_DISPATCH Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 02/23] target-m68k: Build the opcode table only once to avoid multithreading issues Laurent Vivier
2016-10-25 19:02 ` [Qemu-devel] [PULL 03/23] target-m68k: define m680x0 CPUs and features Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 04/23] target-m68k: manage scaled index Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 05/23] target-m68k: introduce read_imXX() functions Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 06/23] target-m68k: set disassembler mode to 680x0 or coldfire Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 07/23] target-m68k: define operand sizes Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 08/23] target-m68k: set PAGE_BITS to 12 for m68k Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 09/23] target-m68k: REG() macro cleanup Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 10/23] target-m68k: allow to update flags with operation on words and bytes Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 11/23] target-m68k: Replace helper_xflag_lt with setcond Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 12/23] target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit() Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 13/23] target-m68k: update move to/from ccr/sr Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 14/23] target-m68k: don't update cc_dest in helpers Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 15/23] target-m68k: update CPU flags management Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 16/23] target-m68k: Print flags properly Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 17/23] target-m68k: Some fixes to SR and flags management Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 18/23] target-m68k: Remove incorrect clearing of cc_x Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 19/23] target-m68k: Reorg flags handling Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 20/23] target-m68k: Introduce DisasCompare Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 21/23] target-m68k: Use setcond for scc Laurent Vivier
2016-10-25 19:03 ` [Qemu-devel] [PULL 22/23] target-m68k: Optimize some comparisons Laurent Vivier
2016-10-25 19:03 ` Laurent Vivier [this message]
2016-10-27 11:45 ` [Qemu-devel] [PULL 00/23] M68k part1 patches Peter Maydell
2016-10-27 11:47 ` Laurent Vivier
2016-10-27 11:50 ` Peter Maydell
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