* [Qemu-devel] [PATCH v2 0/6] POWER9 TCG enablements - part7
@ 2016-10-26 6:24 Nikunj A Dadhania
0 siblings, 0 replies; 2+ messages in thread
From: Nikunj A Dadhania @ 2016-10-26 6:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
This series contains 14 new instructions for POWER9 ISA3.0
VSX Scalar compare
Vector Rotate Left Dword
Vector Rotate Left Word
VSX Vector compare not equal
Vector Parity Byte
Changelog:
v1:
* Simplify extract routines (Richard)
* Added ror/rol fix (Richard)
* Added vector parity and vector compare instructions
v0:
* Use extract32 and extract64 helper (Richard)
* Use rol32 and rol64 helper (Richard)
Patches:
01:
xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision
02:
Fix ror[8,16,32,64] and rol[8,16,32,64]
03:
vrldmi: Vector Rotate Left Dword then Mask Insert
vrlwmi: Vector Rotate Left Word then Mask Insert
04:
vrldnm: Vector Rotate Left Doubleword then AND with Mask
vrlwnm: Vector Rotate Left Word then AND with Mask
05:
vprtybw: Vector Parity Byte Word
vprtybd: Vector Parity Byte Double Word
vprtybq: Vector Parity Byte Quad Word
06:
xvcmpnedp[.]: VSX Vector Compare Not Equal Double-Precision
xvcmpnesp[.]: VSX Vector Compare Not Equal Single-Precision
Ankit Kumar (1):
target-ppc: add vprtyb[w/d/q] instructions
Bharata B Rao (1):
target-ppc: add vrldnm and vrlwnm instructions
Gautham R. Shenoy (1):
target-ppc: add vrldnmi and vrlwmi instructions
Nikunj A Dadhania (1):
bitops: fix rol/ror when shift is zero
Sandipan Das (1):
target-ppc: add xscmp[eq,gt,ge,ne]dp instructions
Swapnil Bokade (1):
target-ppc: Add xvcmpnesp, xvcmpnedp instructions
disas/ppc.c | 4 ++
include/qemu/bitops.h | 16 +++----
target-ppc/fpu_helper.c | 71 +++++++++++++++++++++++++++----
target-ppc/helper.h | 13 ++++++
target-ppc/int_helper.c | 83 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 15 +++++++
target-ppc/translate/vmx-ops.inc.c | 12 ++++--
target-ppc/translate/vsx-impl.inc.c | 6 +++
target-ppc/translate/vsx-ops.inc.c | 6 +++
9 files changed, 206 insertions(+), 20 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread* [Qemu-devel] [PATCH v2 0/6] POWER9 TCG enablements - part7
@ 2016-10-26 6:26 Nikunj A Dadhania
0 siblings, 0 replies; 2+ messages in thread
From: Nikunj A Dadhania @ 2016-10-26 6:26 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, sandipandas1990, ego
This series contains 14 new instructions for POWER9 ISA3.0
VSX Scalar compare
Vector Rotate Left Dword
Vector Rotate Left Word
VSX Vector compare not equal
Vector Parity Byte
Changelog:
v1:
* Simplify extract routines (Richard)
* Added ror/rol fix (Richard)
* Added vector parity and vector compare instructions
v0:
* Use extract32 and extract64 helper (Richard)
* Use rol32 and rol64 helper (Richard)
Patches:
01:
xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision
02:
Fix ror[8,16,32,64] and rol[8,16,32,64]
03:
vrldmi: Vector Rotate Left Dword then Mask Insert
vrlwmi: Vector Rotate Left Word then Mask Insert
04:
vrldnm: Vector Rotate Left Doubleword then AND with Mask
vrlwnm: Vector Rotate Left Word then AND with Mask
05:
vprtybw: Vector Parity Byte Word
vprtybd: Vector Parity Byte Double Word
vprtybq: Vector Parity Byte Quad Word
06:
xvcmpnedp[.]: VSX Vector Compare Not Equal Double-Precision
xvcmpnesp[.]: VSX Vector Compare Not Equal Single-Precision
Ankit Kumar (1):
target-ppc: add vprtyb[w/d/q] instructions
Bharata B Rao (1):
target-ppc: add vrldnm and vrlwnm instructions
Gautham R. Shenoy (1):
target-ppc: add vrldnmi and vrlwmi instructions
Nikunj A Dadhania (1):
bitops: fix rol/ror when shift is zero
Sandipan Das (1):
target-ppc: add xscmp[eq,gt,ge,ne]dp instructions
Swapnil Bokade (1):
target-ppc: Add xvcmpnesp, xvcmpnedp instructions
disas/ppc.c | 4 ++
include/qemu/bitops.h | 16 +++----
target-ppc/fpu_helper.c | 71 +++++++++++++++++++++++++++----
target-ppc/helper.h | 13 ++++++
target-ppc/int_helper.c | 83 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 15 +++++++
target-ppc/translate/vmx-ops.inc.c | 12 ++++--
target-ppc/translate/vsx-impl.inc.c | 6 +++
target-ppc/translate/vsx-ops.inc.c | 6 +++
9 files changed, 206 insertions(+), 20 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread
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