From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzMdZ-0008Nt-SI for qemu-devel@nongnu.org; Wed, 26 Oct 2016 07:44:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzMdX-0005OU-J1 for qemu-devel@nongnu.org; Wed, 26 Oct 2016 07:44:52 -0400 From: David Gibson Date: Wed, 26 Oct 2016 22:42:29 +1100 Message-Id: <1477482173-8761-26-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1477482173-8761-1-git-send-email-david@gibson.dropbear.id.au> References: <1477482173-8761-1-git-send-email-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 25/49] ppc/pnv: add a core mask to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: agraf@suse.de, clg@kaod.org, thuth@redhat.com, lvivier@redhat.com, aik@ozlabs.ru, mark.cave-ayland@ilande.co.uk, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson From: C=C3=A9dric Le Goater This will be used to build real HW ids for the cores and enforce some limits on the available cores per chip. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/ppc/pnv.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++= +++++- include/hw/ppc/pnv.h | 4 +++ 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index aeafd7e..1705699 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -238,11 +238,38 @@ static void ppc_powernv_init(MachineState *machine) object_property_add_child(OBJECT(pnv), chip_name, chip, &error_f= atal); object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", &error_fatal); + object_property_set_int(chip, smp_cores, "nr-cores", &error_fata= l); object_property_set_bool(chip, true, "realized", &error_fatal); } g_free(chip_typename); } =20 +/* Allowed core identifiers on a POWER8 Processor Chip : + * + * + * EX1 - Venice only + * EX2 - Venice only + * EX3 - Venice only + * EX4 + * EX5 + * EX6 + * + * EX9 - Venice only + * EX10 - Venice only + * EX11 - Venice only + * EX12 + * EX13 + * EX14 + * + */ +#define POWER8E_CORE_MASK (0x7070ull) +#define POWER8_CORE_MASK (0x7e7eull) + +/* + * POWER9 has 24 cores, ids starting at 0x20 + */ +#define POWER9_CORE_MASK (0xffffff00000000ull) + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -251,6 +278,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->cpu_model =3D "POWER8E"; k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ + k->cores_mask =3D POWER8E_CORE_MASK; dc->desc =3D "PowerNV Chip POWER8E"; } =20 @@ -269,6 +297,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->cpu_model =3D "POWER8"; k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ + k->cores_mask =3D POWER8_CORE_MASK; dc->desc =3D "PowerNV Chip POWER8"; } =20 @@ -287,6 +316,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->cpu_model =3D "POWER8NVL"; k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ + k->cores_mask =3D POWER8_CORE_MASK; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 @@ -305,6 +335,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->cpu_model =3D "POWER9"; k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ + k->cores_mask =3D POWER9_CORE_MASK; dc->desc =3D "PowerNV Chip POWER9"; } =20 @@ -315,15 +346,55 @@ static const TypeInfo pnv_chip_power9_info =3D { .class_init =3D pnv_chip_power9_class_init, }; =20 +static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + int cores_max; + + /* + * No custom mask for this chip, let's use the default one from * + * the chip class + */ + if (!chip->cores_mask) { + chip->cores_mask =3D pcc->cores_mask; + } + + /* filter alien core ids ! some are reserved */ + if ((chip->cores_mask & pcc->cores_mask) !=3D chip->cores_mask) { + error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64= " !", + chip->cores_mask); + return; + } + chip->cores_mask &=3D pcc->cores_mask; + + /* now that we have a sane layout, let check the number of cores */ + cores_max =3D hweight_long(chip->cores_mask); + if (chip->nr_cores > cores_max) { + error_setg(errp, "warning: too many cores for chip ! Limit is %d= ", + cores_max); + return; + } +} + static void pnv_chip_realize(DeviceState *dev, Error **errp) { - /* left purposely empty */ + PnvChip *chip =3D PNV_CHIP(dev); + Error *error =3D NULL; + + /* Early checks on the core settings */ + pnv_chip_core_sanitize(chip, &error); + if (error) { + error_propagate(errp, error); + return; + } } =20 static Property pnv_chip_properties[] =3D { DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), + DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), + DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7189961..e084a8c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -44,6 +44,9 @@ typedef struct PnvChip { uint32_t chip_id; uint64_t ram_start; uint64_t ram_size; + + uint32_t nr_cores; + uint64_t cores_mask; } PnvChip; =20 typedef struct PnvChipClass { @@ -54,6 +57,7 @@ typedef struct PnvChipClass { const char *cpu_model; PnvChipType chip_type; uint64_t chip_cfam_id; + uint64_t cores_mask; } PnvChipClass; =20 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" --=20 2.7.4