qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry
@ 2016-10-27 11:57 Laurent Vivier
  2016-10-27 13:07 ` Thomas Huth
  0 siblings, 1 reply; 4+ messages in thread
From: Laurent Vivier @ 2016-10-27 11:57 UTC (permalink / raw)
  To: qemu-devel; +Cc: Peter Maydell, Alexander Graf, Laurent Vivier

Add myself to be the M68K maintainer.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b01fec0..7d73748 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -133,7 +133,8 @@ F: include/hw/lm32/
 F: tests/tcg/lm32/
 
 M68K
-S: Orphan
+M: Laurent Vivier <laurent@vivier.eu>
+S: Maintained
 F: target-m68k/
 F: hw/m68k/
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation
@ 2016-05-06 10:06 Alexander Graf
  2016-05-06 10:30 ` [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry Laurent Vivier
  0 siblings, 1 reply; 4+ messages in thread
From: Alexander Graf @ 2016-05-06 10:06 UTC (permalink / raw)
  To: Laurent Vivier, qemu-devel; +Cc: gerg, schwab, rth



On 04.05.16 22:11, Laurent Vivier wrote:
> This series is an update of the series I sent last year:
> 
> https://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg01049.html
> 
> Based on the series sent by Richard Henderson:
> 
> https://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg01793.html
> 
> It is in fact a major rewrite. Most of the instructions are now inlined.
> 
> This series doesn't break Coldfire support. I've checked the following
> image can always boot:
> 
> http://wiki.qemu.org/download/coldfire-test-0.1.tar.bz2
> 
> Only non-privileged instruction are implemented.
> 680x0 FPU instructions are not implemented.
> 
> So this is not enough to run 680x0 binaries. I will send a new series
> with FPU emulation once this series is merged.
> 
> Andreas Schwab (1):
>   target-m68k: terminate cpu dump with newline
> 
> John Paul Adrian Glaubitz (1):
>   target-m68k: Build the opcode table only once to avoid multithreading
>     issues
> 
> Laurent Vivier (39):
>   target-m68k: fix DEBUG_DISPATCH
>   target-m68k: define m680x0 CPUs and features
>   target-m68k: manage scaled index
>   target-m68k: introduce read_imXX() functions
>   target-m68k: set disassembler mode to 680x0 or coldfire
>   target-m68k: add bkpt instruction
>   target-m68k: define operand sizes
>   target-m68k: set PAGE_BITS to 12 for m68k
>   target-m68k: REG() macro cleanup
>   target-m68k: allow to update flags with operation on words and bytes
>   target-m68k: update CPU flags management
>   target-m68k: update move to/from ccr/sr
>   target-m68k: don't update cc_dest in helpers
>   target-m68k: update CPU flags management
>   target-m68k: add addx/subx/negx ops
>   target-m68k: factorize flags computing
>   target-m68k: add scc/dbcc
>   target-m68k: some bit ops cleanup
>   target-m68k: bitfield ops
>   target-m68k: inline divu/divs
>   target-m68k: add 64bit mull
>   target-m68k: inline rotate ops
>   target-m68k: inline shift ops
>   target-m68k: add cas/cas2 ops
>   target-m68k: add linkl
>   target-m68k: movem
>   target-m68k: add exg ops
>   target-m68k: add addressing modes to not
>   target-m68k: eor can manage word and byte operands
>   target-m68k: or can manage word and byte operands
>   target-m68k: and can manage word and byte operands
>   target-m68k: suba/adda can manage word operand
>   target-m68k: introduce byte and word cc_ops
>   target-m68k: add addressing modes to neg
>   target-m68k: add/sub manage word and byte operands
>   target-m68k: cmp manages word and bytes operands
>   target-m68k: immediate ops manage word and byte operands
>   target-m68k: add cmpm
>   target-m68k: sr/ccr cleanup
> 
> Richard Henderson (11):
>   target-m68k: Replace helper_xflag_lt with setcond
>   target-m68k: Print flags properly
>   target-m68k: Some fixes to SR and flags management
>   target-m68k: Remove incorrect clearing of cc_x
>   target-m68k: Reorg flags handling
>   target-m68k: Introduce DisasCompare
>   target-m68k: Use setcond for scc
>   target-m68k: Optimize some comparisons
>   target-m68k: Optimize gen_flush_flags
>   target-m68k: Inline shifts
>   target-m68k: Inline addx, subx, negx
> 
>  cpu-exec.c              |    6 -
>  linux-user/main.c       |  200 +++
>  target-m68k/cpu-qom.h   |    4 -
>  target-m68k/cpu.c       |   65 +-
>  target-m68k/cpu.h       |   83 +-
>  target-m68k/helper.c    |  335 ++---
>  target-m68k/helper.h    |   16 +-
>  target-m68k/op_helper.c |  112 +-
>  target-m68k/qregs.def   |   13 +-
>  target-m68k/translate.c | 3316 +++++++++++++++++++++++++++++++++++++----------

IMHO the most important change would be a patch to the MAINTAINERS file :)


Alex

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-10-27 13:07 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-10-27 11:57 [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry Laurent Vivier
2016-10-27 13:07 ` Thomas Huth
  -- strict thread matches above, loose matches on Subject: below --
2016-05-06 10:06 [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation Alexander Graf
2016-05-06 10:30 ` [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry Laurent Vivier
2016-05-12  7:55   ` Thomas Huth

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).