From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: schwab@linux-m68k.org, agraf@suse.de,
Richard Henderson <rth@twiddle.net>,
gerg@uclinux.org, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 0/3] 680x0 instruction set, part 2
Date: Thu, 27 Oct 2016 21:09:51 +0200 [thread overview]
Message-ID: <1477595394-23807-1-git-send-email-laurent@vivier.eu> (raw)
This series is another subset of the series I sent in May:
https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg00501.html
It must be applied on top of series:
"target-m68k: 680x0 instruction set, part 1"
This subset contains reworked patches for:
- cmpm, delay the writeback of the value of the register
after the second load to avoid problem with page fault,
- shift instruction, compute V flags as advised by Richard
I've checked it doesn't break coldfire support:
http://wiki.qemu.org/download/coldfire-test-0.1.tar.bz2
but it can't boot a 680x0 processor kernel.
Laurent Vivier (2):
target-m68k: add cmpm
target-m68k: shift ops manage word and byte operands
Richard Henderson (1):
target-m68k: Inline shifts
target-m68k/helper.c | 52 ----------
target-m68k/helper.h | 3 -
target-m68k/translate.c | 261 +++++++++++++++++++++++++++++++++++++++++++-----
3 files changed, 235 insertions(+), 81 deletions(-)
--
2.7.4
next reply other threads:[~2016-10-27 19:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-27 19:09 Laurent Vivier [this message]
2016-10-27 19:09 ` [Qemu-devel] [PATCH 1/3] target-m68k: add cmpm Laurent Vivier
2016-10-27 19:47 ` Richard Henderson
2016-10-27 19:09 ` [Qemu-devel] [PATCH 2/3] target-m68k: Inline shifts Laurent Vivier
2016-10-27 19:09 ` [Qemu-devel] [PATCH 3/3] target-m68k: shift ops manage word and byte operands Laurent Vivier
2016-10-27 20:07 ` Richard Henderson
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