From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54800) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzq47-0002jC-TJ for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzq42-0001Dn-VS for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:15 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:51139) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzq42-0001CU-L8 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:10 -0400 From: Laurent Vivier Date: Thu, 27 Oct 2016 21:09:51 +0200 Message-Id: <1477595394-23807-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 0/3] 680x0 instruction set, part 2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: schwab@linux-m68k.org, agraf@suse.de, Richard Henderson , gerg@uclinux.org, Laurent Vivier This series is another subset of the series I sent in May: https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg00501.html It must be applied on top of series: "target-m68k: 680x0 instruction set, part 1" This subset contains reworked patches for: - cmpm, delay the writeback of the value of the register after the second load to avoid problem with page fault, - shift instruction, compute V flags as advised by Richard I've checked it doesn't break coldfire support: http://wiki.qemu.org/download/coldfire-test-0.1.tar.bz2 but it can't boot a 680x0 processor kernel. Laurent Vivier (2): target-m68k: add cmpm target-m68k: shift ops manage word and byte operands Richard Henderson (1): target-m68k: Inline shifts target-m68k/helper.c | 52 ---------- target-m68k/helper.h | 3 - target-m68k/translate.c | 261 +++++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 235 insertions(+), 81 deletions(-) -- 2.7.4