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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, clg@kaod.org, thuth@redhat.com,
	lvivier@redhat.com, aik@ozlabs.ru, mark.cave-ayland@ilande.co.uk,
	mdroth@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 15/73] target-ppc: implement xxbr[qdwh] instruction
Date: Fri, 28 Oct 2016 12:37:16 +1100	[thread overview]
Message-ID: <1477618694-21019-16-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1477618694-21019-1-git-send-email-david@gibson.dropbear.id.au>

From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Add required helpers (GEN_XX2FORM_EO) for supporting this instruction.

xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector Byte-Reverse Doubleword
xxbrq: VSX Vector Byte-Reverse Quadword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate.c              | 32 +++++++++++++++
 target-ppc/translate/vsx-impl.inc.c | 77 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  8 ++++
 3 files changed, 117 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index dab8f19..94989b2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -376,6 +376,9 @@ GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
 
+#define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
+GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
+
 typedef struct opcode_t {
     unsigned char opc1, opc2, opc3, opc4;
 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
@@ -662,6 +665,21 @@ EXTRACT_HELPER(IMM8, 11, 8);
     },                                                                        \
     .oname = stringify(name),                                                 \
 }
+#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
+{                                                                             \
+    .opc1 = op1,                                                              \
+    .opc2 = op2,                                                              \
+    .opc3 = op3,                                                              \
+    .opc4 = op4,                                                              \
+    .handler = {                                                              \
+        .inval1  = invl,                                                      \
+        .type = _typ,                                                         \
+        .type2 = _typ2,                                                       \
+        .handler = &gen_##name,                                               \
+        .oname = onam,                                                        \
+    },                                                                        \
+    .oname = onam,                                                            \
+}
 #else
 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
 {                                                                             \
@@ -720,6 +738,20 @@ EXTRACT_HELPER(IMM8, 11, 8);
     },                                                                        \
     .oname = stringify(name),                                                 \
 }
+#define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
+{                                                                             \
+    .opc1 = op1,                                                              \
+    .opc2 = op2,                                                              \
+    .opc3 = op3,                                                              \
+    .opc4 = op4,                                                              \
+    .handler = {                                                              \
+        .inval1  = invl,                                                      \
+        .type = _typ,                                                         \
+        .type2 = _typ2,                                                       \
+        .handler = &gen_##name,                                               \
+    },                                                                        \
+    .oname = onam,                                                            \
+}
 #endif
 
 /* SPR load/store helpers */
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 23ec1e1..1508bd1 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -132,6 +132,22 @@ static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
     tcg_temp_free_i64(mask);
 }
 
+static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
+                          TCGv_i64 inh, TCGv_i64 inl)
+{
+    TCGv_i64 hi = tcg_temp_new_i64();
+    TCGv_i64 lo = tcg_temp_new_i64();
+
+    tcg_gen_bswap64_i64(hi, inh);
+    tcg_gen_bswap64_i64(lo, inl);
+    tcg_gen_shri_i64(outh, hi, 32);
+    tcg_gen_deposit_i64(outh, outh, hi, 32, 32);
+    tcg_gen_shri_i64(outl, lo, 32);
+    tcg_gen_deposit_i64(outl, outl, lo, 32, 32);
+
+    tcg_temp_free_i64(hi);
+    tcg_temp_free_i64(lo);
+}
 static void gen_lxvh8x(DisasContext *ctx)
 {
     TCGv EA;
@@ -717,6 +733,67 @@ GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
 
+static void gen_xxbrd(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    tcg_gen_bswap64_i64(xth, xbh);
+    tcg_gen_bswap64_i64(xtl, xbl);
+}
+
+static void gen_xxbrh(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_bswap16x8(xth, xtl, xbh, xbl);
+}
+
+static void gen_xxbrq(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+    TCGv_i64 t0 = tcg_temp_new_i64();
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    tcg_gen_bswap64_i64(t0, xbl);
+    tcg_gen_bswap64_i64(xtl, xbh);
+    tcg_gen_mov_i64(xth, t0);
+    tcg_temp_free_i64(t0);
+}
+
+static void gen_xxbrw(DisasContext *ctx)
+{
+    TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+    TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+    TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+    TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_bswap32x4(xth, xtl, xbh, xbl);
+}
+
 #define VSX_LOGICAL(name, tcg_op)                                    \
 static void glue(gen_, name)(DisasContext * ctx)                     \
     {                                                                \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 10eb4b9..af0d27e 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -39,6 +39,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
 
+#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)                          \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
+
 #define GEN_XX3FORM(name, opc2, opc3, fl2)                           \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
@@ -222,6 +226,10 @@ GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
+GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
 
 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
 GEN_XX3FORM(name, opc2, opc3, fl2)
-- 
2.7.4

  parent reply	other threads:[~2016-10-28  1:39 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-28  1:37 [Qemu-devel] [PULL 00/73] ppc-for-2.8 queue 20161028 David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 01/73] pseries: Update SLOF firmware image to 20161019 David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 02/73] ppc/xics: Add xics to the monitor "info pic" command David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 03/73] tests: fix memory leak in virtio-scsi-test David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 04/73] tests: don't check if qtest_spapr_boot() returns NULL David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 05/73] tests: move QVirtioBus pointer into QVirtioDevice David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 06/73] tests: rename target_big_endian() as qvirtio_is_big_endian() David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 07/73] tests: use qtest_pc_boot()/qtest_shutdown() in virtio tests David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 08/73] tests: enable virtio tests on SPAPR David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 09/73] spapr_pci: advertise explicit numa IDs even when there's 1 node David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 10/73] nvram: Introduce helper functions for CHRP "system" and "free space" partitions David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 11/73] sparc: Use the new common NVRAM functions for system and free space partition David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 12/73] nvram: Move the remaining CHRP NVRAM related code to chrp_nvram.[ch] David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 13/73] nvram: Rename openbios_firmware_abi.h into sun_nvram.h David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 14/73] target-ppc: implement vnegw/d instructions David Gibson
2016-10-28  1:37 ` David Gibson [this message]
2016-10-28  1:37 ` [Qemu-devel] [PULL 16/73] ppc/xics: add a xics_set_nr_servers common routine David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 17/73] ppc/xics: add a XICSState backlink in ICPState David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 18/73] ppc/xics: change the icp_ routines API to use an 'ICPState *' argument David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 19/73] ppc: fix MSR_ME handling for system reset interrupt David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 20/73] pseries: Remove unused callbacks from sPAPR VIO bus state David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 21/73] ppc: Fix single step with gdb stub David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 22/73] ppc: add skiboot firmware for the pnv platform David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 23/73] configure, ppc64: Copy skiboot.lid to build directory when configuring David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 24/73] ppc/pnv: add skeleton PowerNV platform David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 25/73] ppc/pnv: add a PnvChip object David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 26/73] ppc/pnv: add a core mask to PnvChip David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 27/73] ppc/pnv: add a PIR handler " David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 28/73] ppc/pnv: add a PnvCore object David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 29/73] ppc/pnv: add XSCOM infrastructure David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 30/73] ppc/pnv: add XSCOM handlers to PnvCore David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 31/73] ppc/pnv: add a LPC controller David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 32/73] ppc/pnv: add a ISA bus David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 33/73] target-ppc: add vmul10[u, eu, cu, ecu]q instructions David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 34/73] pseries: Split device tree construction from device tree load David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 35/73] pseries: Remove rtas_addr and fdt_addr fields from machinestate David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 36/73] pseries: Make spapr_create_fdt_skel() get information from machine state David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 37/73] pseries: Move adding of fdt reserve map entries David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 38/73] pseries: Consolidate RTAS loading David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 39/73] pseries: Move construction of /interrupt-controller fdt node David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 40/73] pseries: Consolidate construction of /chosen device tree node David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 41/73] pseries: Consolidate construction of /rtas " David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 42/73] pseries: Move /event-sources construction to spapr_build_fdt() David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 43/73] pseries: Move /hypervisor node construction to fdt_build_fdt() David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 44/73] pseries: Consolidate construction of /vdevice device tree node David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 45/73] pseries: Remove spapr_create_fdt_skel() David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 46/73] spapr_ovec: initial implementation of option vector helpers David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 47/73] spapr_hcall: use spapr_ovec_* interfaces for CAS options David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 48/73] spapr: add option vector handling in CAS-generated resets David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 49/73] spapr: improve ibm, architecture-vec-5 property handling David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 50/73] adb: change handler only when recognized David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 51/73] libqos: Give qvirtio_config_read*() consistent semantics David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 52/73] libqos: Handle PCI IO de-multiplexing in common code David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 53/73] libqos: Move BAR assignment to " David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 54/73] libqos: Better handling of PCI legacy IO David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 55/73] tests: Adjust tco-test to use qpci_legacy_iomap() David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 56/73] libqos: Add streaming accessors for PCI MMIO David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 57/73] libqos: Implement mmio accessors in terms of mem{read, write} David Gibson
2016-10-28  1:37 ` [Qemu-devel] [PULL 58/73] tests: Clean up IO handling in ide-test David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 59/73] libqos: Add 64-bit PCI IO accessors David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 60/73] tests: Use qpci_mem{read, write} in ivshmem-test David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 61/73] tests: Don't assume structure of PCI IO base in ahci-test David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 62/73] libqos: Change PCI accessors to take opaque BAR handle David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 63/73] spapr_nvram: Pre-initialize the NVRAM to support the -prom-env parameter David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 64/73] tests: Add pseries machine to the prom-env-test, too David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 65/73] target-ppc: add xscmp[eq, gt, ge, ne]dp instructions David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 66/73] target-ppc: Add xvcmpnesp, xvcmpnedp instructions David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 67/73] spapr: update spapr hotplug documentation David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 68/73] spapr_events: add support for dedicated hotplug event source David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 69/73] spapr: add hotplug interrupt machine options David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 70/73] spapr: Add DRC count indexed hotplug identifier type David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 71/73] spapr: use count+index for memory hotplug David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 72/73] spapr: Memory hot-unplug support David Gibson
2016-10-28  1:38 ` [Qemu-devel] [PULL 73/73] ppc: allow certain HV interrupts to be delivered to guests David Gibson
2016-10-28 16:22 ` [Qemu-devel] [PULL 00/73] ppc-for-2.8 queue 20161028 Peter Maydell

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