[Qemu-devel] [PULL 0/9] target-arm queue

[Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

target-arm queue. I'm expecting to do another queue run before
hard freeze, since there are still some bits and pieces on
list which need a little more review before they can be
committed.

thanks
-- PMM

The following changes since commit e9d818b8b1a7fadc6c92256b716f1bc21b8daabc:

  Merge remote-tracking branch 'remotes/rth/tcg-aarch-6-1' into staging (2014-03-10 12:34:41 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140310

for you to fetch changes up to 72c1d3af6e9c2745edfeaa71918a68bcee4b79db:

  target-arm: Implement WFE as a yield operation (2014-03-10 14:56:30 +0000)

----------------------------------------------------------------
target-arm queue:
 * implement WFE as yield (improves performance with emulated SMP)
 * fixes to avoid undefined behaviour shifting left into sign bit
 * libvixl format string fixes for 32 bit hosts
 * fix build error when intptr_t and tcg_target_long are different
   sizes (eg x32)
 * implement PMCCNTR register
 * fix incorrect setting of E bit in CPSR (broke booting under
   KVM on ARM)

----------------------------------------------------------------
Alistair Francis (1):
      target-arm: Implements the ARM PMCCNTR register

Peter Maydell (6):
      target-arm: Fix incorrect setting of E bit in CPSR
      pxa2xx: Don't shift into sign bit
      hw/arm/omap1.c: Avoid shifting left into sign bit
      hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit
      hw/arm/musicpal: Avoid shifting left into sign bit
      target-arm: Implement WFE as a yield operation

Richard Henderson (1):
      target-arm: Fix intptr_t vs tcg_target_long

Stefan Weil (1):
      libvixl: Fix format strings for several int64_t values

 disas/libvixl/a64/disasm-a64.cc | 20 ++++-----
 hw/arm/musicpal.c               |  4 +-
 hw/arm/omap1.c                  | 24 ++++++-----
 hw/arm/pxa2xx.c                 |  6 +--
 hw/arm/pxa2xx_gpio.c            |  2 +-
 hw/arm/pxa2xx_pic.c             |  4 +-
 hw/ssi/xilinx_spips.c           |  4 +-
 include/exec/cpu-defs.h         |  1 +
 target-arm/cpu.h                |  4 ++
 target-arm/helper.c             | 91 ++++++++++++++++++++++++++++++++++++++---
 target-arm/helper.h             |  1 +
 target-arm/op_helper.c          |  9 ++++
 target-arm/translate-a64.c      |  2 +-
 target-arm/translate.c          |  6 +++
 target-arm/translate.h          |  2 +
 15 files changed, 144 insertions(+), 36 deletions(-)

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

On 10 March 2014 15:09, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue. I'm expecting to do another queue run before
> hard freeze, since there are still some bits and pieces on
> list which need a little more review before they can be
> committed.
>
> thanks
> -- PMM
>
> The following changes since commit e9d818b8b1a7fadc6c92256b716f1bc21b8daabc:
>
>   Merge remote-tracking branch 'remotes/rth/tcg-aarch-6-1' into staging (2014-03-10 12:34:41 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140310
>
> for you to fetch changes up to 72c1d3af6e9c2745edfeaa71918a68bcee4b79db:
>
>   target-arm: Implement WFE as a yield operation (2014-03-10 14:56:30 +0000)
>

Applied to master, thanks.

-- PMM

[Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

Mostly just bugfixes that accumulated over the course of
the week; the only new feature in here is the 'pmu'
property patches for the virt board.

thanks
-- PMM


The following changes since commit fd209e4a773dd5a7fea79eaaffd276ebcb99e92a:

  Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2016-10-28 14:29:50 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161028

for you to fetch changes up to d26a10e232eb18bf9e32dc2366231715bfd1d5b4:

  hw/arm/tosa: Fix reset handling (2016-10-28 15:51:27 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix reset GPIO handling for spitz, tosa boards
 * virt: add 'pmu' property for configuring whether to expose the
   vPMU to the guest
 * char: cadence: correct reset value for baud rate registers
 * versatilepb: do not run if user asks for more than 256MB RAM
 * pxa2xx: Set value default values for CCCR and CKEN on PXA255
 * arm: cubieboard: Add support for initrd
 * i.MX: Fix GPIO ISR register write

----------------------------------------------------------------
Guenter Roeck (5):
      i.MX: Fix GPIO ISR register write
      arm: cubieboard: Add support for initrd
      hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255
      hw/arm/spitz: Fix reset handling
      hw/arm/tosa: Fix reset handling

Jean-Christophe Dubois (1):
      versatilepb: do not run if user asks for more than 256MB RAM

Prasad J Pandit (1):
      char: cadence: correct reset value for baud rate registers

Wei Huang (2):
      arm: Add an option to turn on/off vPMU support
      arm: virt: add PMU property to mach-virt machine type

 hw/arm/cubieboard.c      |  1 +
 hw/arm/pxa2xx.c          |  4 +++-
 hw/arm/spitz.c           | 13 ++++++++++++-
 hw/arm/tosa.c            | 12 +++++++++++-
 hw/arm/versatilepb.c     |  9 +++++++++
 hw/arm/virt-acpi-build.c |  2 +-
 hw/arm/virt.c            |  9 ++++++++-
 hw/char/cadence_uart.c   |  3 ++-
 hw/gpio/imx_gpio.c       |  2 +-
 target-arm/cpu.c         | 15 +++++++++++++++
 target-arm/cpu.h         |  1 +
 target-arm/cpu64.c       |  2 ++
 target-arm/kvm64.c       | 17 ++++++++++++++---
 13 files changed, 80 insertions(+), 10 deletions(-)

[Qemu-devel] [PULL 1/9] i.MX: Fix GPIO ISR register write

[Peter Maydell]

From: Guenter Roeck <linux@roeck-us.net>

Writing the ISR register is supposed to clear interrupt status bits,
not to set them.

This patch makes '-M sabrelite' work without devicetree changes (Linux
kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
multi_v7_defconfig; mainline has different problems).

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1477361005-18646-1-git-send-email-linux@roeck-us.net
Acked-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/imx_gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index f3574aa..c36c394 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
         break;
 
     case ISR_ADDR:
-        s->isr |= ~value;
+        s->isr &= ~value;
         imx_gpio_set_all_int_lines(s);
         break;
 
-- 
2.7.4

[Qemu-devel] [PULL 2/9] arm: cubieboard: Add support for initrd

[Peter Maydell]

From: Guenter Roeck <linux@roeck-us.net>

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1477361131-18752-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/cubieboard.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index fbd78ed..dd19ba3 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -74,6 +74,7 @@ static void cubieboard_init(MachineState *machine)
     cubieboard_binfo.ram_size = machine->ram_size;
     cubieboard_binfo.kernel_filename = machine->kernel_filename;
     cubieboard_binfo.kernel_cmdline = machine->kernel_cmdline;
+    cubieboard_binfo.initrd_filename = machine->initrd_filename;
     arm_load_kernel(&s->a10->cpu, &cubieboard_binfo);
 }
 
-- 
2.7.4

[Qemu-devel] [PULL 3/9] hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255

[Peter Maydell]

From: Guenter Roeck <linux@roeck-us.net>

The code used default values for PXA270 to configure CCCR. For PXA255,
the resulting register value is invalid (unsupported) and resulted
in a division by zero in the Linux kernel. Use default values from
datasheet instead.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1477361273-18888-1-git-send-email-linux@roeck-us.net
[PMM: fixed tabs-vs-spaces nit]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/pxa2xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 42cdde0..21ea1d6 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2267,7 +2267,9 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
                     qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
 
     s->cm_base = 0x41300000;
-    s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
+    s->cm_regs[CCCR >> 2] = 0x00000121;         /* from datasheet */
+    s->cm_regs[CKEN >> 2] = 0x00017def;         /* from datasheet */
+
     s->clkcfg = 0x00000009;		/* Turbo mode active */
     memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
     memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
-- 
2.7.4

[Qemu-devel] [PULL 4/9] versatilepb: do not run if user asks for more than 256MB RAM

[Peter Maydell]

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The versatilepb physical address space layout only has
a 256MB region for RAM before the devices. Without a guard
on the amount of RAM requested by the user we would happily
create a RAM area that overlapped with the devices, resulting
in very confusing behaviour (typically a guest crash).

Report the problem to the user if they try to request more
RAM than the board can handle (as we do already for some
other board models).

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 20161025093711.17407-1-jcd@tribudubois.net
[PMM: tidied up commit message, comments. Use error_report()
 rather than fprintf(stderr, ...).]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/versatilepb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 8ae5392..7b5cb36 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -198,6 +198,15 @@ static void versatile_init(MachineState *machine, int board_id)
     int done_smc = 0;
     DriveInfo *dinfo;
 
+    if (machine->ram_size > 0x10000000) {
+        /* Device starting at address 0x10000000,
+         * and memory cannot overlap with devices.
+         * Refuse to run rather than behaving very confusingly.
+         */
+        error_report("versatilepb: memory size must not exceed 256MB");
+        exit(1);
+    }
+
     if (!machine->cpu_model) {
         machine->cpu_model = "arm926";
     }
-- 
2.7.4

[Qemu-devel] [PULL 5/9] char: cadence: correct reset value for baud rate registers

[Peter Maydell]

From: Prasad J Pandit <pjp@fedoraproject.org>

The Cadence UART device emulator stores 'baud rate generator'
and 'baud rate divider' values, used in computing speed, in two
registers. The device specification defines their range and
their reset value. Use their correct value when resetting the
device in cadence_uart_reset.

Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-id: 1477378140-2670-1-git-send-email-ppandit@redhat.com
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/cadence_uart.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index c2b9154..def34cd 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -450,7 +450,8 @@ static void cadence_uart_reset(DeviceState *dev)
     s->r[R_IMR] = 0;
     s->r[R_CISR] = 0;
     s->r[R_RTRIG] = 0x00000020;
-    s->r[R_BRGR] = 0x0000000F;
+    s->r[R_BRGR] = 0x0000028B;
+    s->r[R_BDIV] = 0x0000000F;
     s->r[R_TTRIG] = 0x00000020;
 
     uart_rx_reset(s);
-- 
2.7.4

[Qemu-devel] [PULL 6/9] arm: Add an option to turn on/off vPMU support

[Peter Maydell]

From: Wei Huang <wei@redhat.com>

This patch adds a pmu=[on/off] option to enable/disable vPMU support
in guest vCPU. It allows virt tools, such as libvirt, to determine the
exsitence of vPMU and configure it. Note this option is only available
for cortex-a57/cortex-53/ host CPUs, but unavailable on ARMv7 and other
processors. Also even though "pmu=" option is available for TCG mode,
setting it doesn't turn PMU on.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 1477463301-17175-2-git-send-email-wei@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c |  2 +-
 hw/arm/virt.c            |  2 +-
 target-arm/cpu.c         | 15 +++++++++++++++
 target-arm/cpu.h         |  1 +
 target-arm/cpu64.c       |  2 ++
 target-arm/kvm64.c       | 17 ++++++++++++++---
 6 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 5fc10df..f953610 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -594,7 +594,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
         gicc->uid = i;
         gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 
-        if (armcpu->has_pmu) {
+        if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
             gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
         }
     }
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 070bbf8..32c95fb 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -490,7 +490,7 @@ static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
 
     CPU_FOREACH(cpu) {
         armcpu = ARM_CPU(cpu);
-        if (!armcpu->has_pmu ||
+        if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||
             !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
             return;
         }
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2439ca5..99f0dbe 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "qapi/error.h"
 #include "cpu.h"
 #include "internals.h"
@@ -496,6 +497,10 @@ static Property arm_cpu_rvbar_property =
 static Property arm_cpu_has_el3_property =
             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 
+/* use property name "pmu" to match other archs and virt tools */
+static Property arm_cpu_has_pmu_property =
+            DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
+
 static Property arm_cpu_has_mpu_property =
             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 
@@ -539,6 +544,11 @@ static void arm_cpu_post_init(Object *obj)
 #endif
     }
 
+    if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
+        qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
+                                 &error_abort);
+    }
+
     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
                                  &error_abort);
@@ -677,6 +687,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->id_aa64pfr0 &= ~0xf000;
     }
 
+    if (!cpu->has_pmu || !kvm_enabled()) {
+        cpu->has_pmu = false;
+        unset_feature(env, ARM_FEATURE_PMU);
+    }
+
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
         /* Disable the hypervisor feature bits in the processor feature
          * registers if we don't have EL2. These are id_pfr1[15:12] and
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 19d967b..ca5c849 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1124,6 +1124,7 @@ enum arm_features {
     ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
     ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
+    ARM_FEATURE_PMU, /* has PMU support */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 1635deb..549cb1e 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -111,6 +111,7 @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
     cpu->midr = 0x411fd070;
     cpu->revidr = 0x00000000;
@@ -166,6 +167,7 @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
     cpu->midr = 0x410fd034;
     cpu->revidr = 0x00000000;
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 5faa76c..6111109 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -428,6 +428,11 @@ static inline void set_feature(uint64_t *features, int feature)
     *features |= 1ULL << feature;
 }
 
+static inline void unset_feature(uint64_t *features, int feature)
+{
+    *features &= ~(1ULL << feature);
+}
+
 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
 {
     /* Identify the feature bits corresponding to the host CPU, and
@@ -469,6 +474,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
     set_feature(&features, ARM_FEATURE_VFP4);
     set_feature(&features, ARM_FEATURE_NEON);
     set_feature(&features, ARM_FEATURE_AARCH64);
+    set_feature(&features, ARM_FEATURE_PMU);
 
     ahcc->features = features;
 
@@ -482,6 +488,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
     int ret;
     uint64_t mpidr;
     ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
 
     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
@@ -501,10 +508,14 @@ int kvm_arch_init_vcpu(CPUState *cs)
     if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
     }
-    if (kvm_irqchip_in_kernel() &&
-        kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
-        cpu->has_pmu = true;
+    if (!kvm_irqchip_in_kernel() ||
+        !kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
+            cpu->has_pmu = false;
+    }
+    if (cpu->has_pmu) {
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
+    } else {
+        unset_feature(&env->features, ARM_FEATURE_PMU);
     }
 
     /* Do KVM_ARM_VCPU_INIT ioctl */
-- 
2.7.4

[Qemu-devel] [PULL 7/9] arm: virt: add PMU property to mach-virt machine type

[Peter Maydell]

From: Wei Huang <wei@redhat.com>

CPU vPMU is now turned ON by default, but this feature wasn't introduced
until virt-2.7 machine type. To solve this problem, this patch adds a
PMU option in machine state, which is used to control CPU's vPMU status.
This PMU option is not exposed to command line and is turned off in
virt-2.6 machine type.

Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Wei Huang <wei@redhat.com>
Message-id: 1477463301-17175-3-git-send-email-wei@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 32c95fb..54a8b28 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -85,6 +85,7 @@ typedef struct {
     VirtBoardInfo *daughterboard;
     bool disallow_affinity_adjustment;
     bool no_its;
+    bool no_pmu;
 } VirtMachineClass;
 
 typedef struct {
@@ -1353,6 +1354,10 @@ static void machvirt_init(MachineState *machine)
             }
         }
 
+        if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
+            object_property_set_bool(cpuobj, false, "pmu", NULL);
+        }
+
         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
             object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base,
                                     "reset-cbar", &error_abort);
@@ -1592,5 +1597,7 @@ static void virt_machine_2_6_options(MachineClass *mc)
     virt_machine_2_7_options(mc);
     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
     vmc->disallow_affinity_adjustment = true;
+    /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
+    vmc->no_pmu = true;
 }
 DEFINE_VIRT_MACHINE(2, 6)
-- 
2.7.4

[Qemu-devel] [PULL 8/9] hw/arm/spitz: Fix reset handling

[Peter Maydell]

From: Guenter Roeck <linux@roeck-us.net>

Using the CPU reset handler for resets triggered by writing into
gpio pins other than GPIO01 is not appropriate and does not work,
since the reset triggered by writing into GPIO01 is configurable.
Use a separate reset handler for spitz to reset the entire system
and not just the CPU.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1477597646-24111-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/spitz.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 41cc2ee..949a15a 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -29,6 +29,7 @@
 #include "sysemu/block-backend.h"
 #include "hw/sysbus.h"
 #include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
 
 #undef REG_FMT
 #define REG_FMT			"0x%02lx"
@@ -844,9 +845,18 @@ static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
     spitz_hsync ^= 1;
 }
 
+static void spitz_reset(void *opaque, int line, int level)
+{
+    if (level) {
+        qemu_system_reset_request();
+    }
+}
+
 static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 {
     qemu_irq lcd_hsync;
+    qemu_irq reset;
+
     /*
      * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
      * read to satisfy broken guests that poll-wait for hsync.
@@ -867,7 +877,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
     qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
 
     /* Handle reset */
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
+    reset = qemu_allocate_irq(spitz_reset, cpu, 0);
+    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, reset);
 
     /* PCMCIA signals: card's IRQ and Card-Detect */
     if (slots >= 1)
-- 
2.7.4

[Qemu-devel] [PULL 9/9] hw/arm/tosa: Fix reset handling

[Peter Maydell]

From: Guenter Roeck <linux@roeck-us.net>

Using the CPU reset handler for resets triggered by writing into
gpio pins other than GPIO01 is not appropriate and does not work,
since the reset triggered by writing into GPIO01 is configurable.
Use a separate reset handler for tosa to reset the entire system
and not just the CPU.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1477597646-24111-2-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/tosa.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 2db6650..1ee12f4 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -25,6 +25,7 @@
 #include "sysemu/block-backend.h"
 #include "hw/sysbus.h"
 #include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
 
 #define TOSA_RAM    0x04000000
 #define TOSA_ROM	0x00800000
@@ -86,6 +87,12 @@ static void tosa_out_switch(void *opaque, int line, int level)
     }
 }
 
+static void tosa_reset(void *opaque, int line, int level)
+{
+    if (level) {
+        qemu_system_reset_request();
+    }
+}
 
 static void tosa_gpio_setup(PXA2xxState *cpu,
                 DeviceState *scp0,
@@ -93,13 +100,16 @@ static void tosa_gpio_setup(PXA2xxState *cpu,
                 TC6393xbState *tmio)
 {
     qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
+    qemu_irq reset;
+
     /* MMC/SD host */
     pxa2xx_mmci_handlers(cpu->mmc,
                     qdev_get_gpio_in(scp0, TOSA_GPIO_SD_WP),
                     qemu_irq_invert(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_nSD_DETECT)));
 
     /* Handle reset */
-    qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, cpu->reset);
+    reset = qemu_allocate_irq(tosa_reset, cpu, 0);
+    qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, reset);
 
     /* PCMCIA signals: card's IRQ and Card-Detect */
     pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
-- 
2.7.4

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

On 28 October 2016 at 15:59, Peter Maydell <peter.maydell@linaro.org> wrote:
> Mostly just bugfixes that accumulated over the course of
> the week; the only new feature in here is the 'pmu'
> property patches for the virt board.
>
> thanks
> -- PMM
>
>
> The following changes since commit fd209e4a773dd5a7fea79eaaffd276ebcb99e92a:
>
>   Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2016-10-28 14:29:50 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161028
>
> for you to fetch changes up to d26a10e232eb18bf9e32dc2366231715bfd1d5b4:
>
>   hw/arm/tosa: Fix reset handling (2016-10-28 15:51:27 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Fix reset GPIO handling for spitz, tosa boards
>  * virt: add 'pmu' property for configuring whether to expose the
>    vPMU to the guest
>  * char: cadence: correct reset value for baud rate registers
>  * versatilepb: do not run if user asks for more than 256MB RAM
>  * pxa2xx: Set value default values for CCCR and CKEN on PXA255
>  * arm: cubieboard: Add support for initrd
>  * i.MX: Fix GPIO ISR register write

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

ARM bugfixes for rc1...


The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:

  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113

for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:

  accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)

----------------------------------------------------------------
target-arm queue:
 * translate-a64.c: silence gcc5 warning
 * highbank: validate register offset before access
 * MAINTAINERS: Add entries for Smartfusion2
 * accel/tcg/translate-all: expand cpu_restore_state addr check
   (so usermode insn aborts don't crash with an assertion failure)
 * fix TCG initialization of some Arm boards by allowing them
   to specify min/default number of CPUs to create

----------------------------------------------------------------
Alex Bennée (1):
      accel/tcg/translate-all: expand cpu_restore_state addr check

Alistair Francis (2):
      xlnx-zynqmp: Properly support the smp command line option
      xlnx-zcu102: Add an info message deprecating the EP108

Emilio G. Cota (4):
      arm/translate-a64: mark path as unreachable to eliminate warning
      qom: move CPUClass.tcg_initialize to a global
      xlnx-zcu102: Specify the max number of CPUs for the EP108
      hw: add .min_cpus and .default_cpus fields to machine_class

Prasad J Pandit (1):
      highbank: validate register offset before access

Subbaraya Sundeep (1):
      MAINTAINERS: Add entries for Smartfusion2

 include/exec/exec-all.h    | 11 ++++++++++
 include/hw/boards.h        |  5 +++++
 include/qom/cpu.h          |  1 -
 accel/tcg/translate-all.c  | 52 ++++++++++++++++++++++++++--------------------
 exec.c                     |  5 +++--
 hw/arm/exynos4_boards.c    | 12 ++++-------
 hw/arm/highbank.c          | 17 +++++++++++++--
 hw/arm/raspi.c             |  2 ++
 hw/arm/xlnx-zcu102.c       |  9 +++++++-
 hw/arm/xlnx-zynqmp.c       | 26 ++++++++++++++---------
 target/arm/translate-a64.c |  2 ++
 vl.c                       | 21 ++++++++++++++++---
 MAINTAINERS                | 17 +++++++++++++++
 qemu-doc.texi              |  7 +++++++
 14 files changed, 137 insertions(+), 50 deletions(-)

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

On 13 November 2017 at 14:11, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM bugfixes for rc1...
>
>
> The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:
>
>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113
>
> for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:
>
>   accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * translate-a64.c: silence gcc5 warning
>  * highbank: validate register offset before access
>  * MAINTAINERS: Add entries for Smartfusion2
>  * accel/tcg/translate-all: expand cpu_restore_state addr check
>    (so usermode insn aborts don't crash with an assertion failure)
>  * fix TCG initialization of some Arm boards by allowing them
>    to specify min/default number of CPUs to create
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

A last collection of patches to squeeze in before rc0.
The patches from me are all bugfixes. Philippe's are just
code-movement, but I wanted to get these into 4.1 because
that kind of patch is so painful to have to rebase.
(The diffstat is huge but it's just code moving from file to file.)

thanks
-- PMM

The following changes since commit 234e256511e588680300600ce087c5185d68cf2a:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-build-2019-07-02-v2' into staging (2019-07-04 15:58:46 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190704

for you to fetch changes up to b75f3735802b5b33f10e4bfe374d4b17bb86d29a:

  target/arm: Correct VMOV_imm_dp handling of short vectors (2019-07-04 16:52:05 +0100)

----------------------------------------------------------------
target-arm queue:
 * more code-movement to separate TCG-only functions into their own files
 * Correct VMOV_imm_dp handling of short vectors
 * Execute Thumb instructions when their condbits are 0xf
 * armv7m_systick: Forbid non-privileged accesses
 * Use _ra versions of cpu_stl_data() in v7M helpers
 * v8M: Check state of exception being returned from
 * v8M: Forcibly clear negative-priority exceptions on deactivate

----------------------------------------------------------------
Peter Maydell (6):
      arm v8M: Forcibly clear negative-priority exceptions on deactivate
      target/arm: v8M: Check state of exception being returned from
      target/arm: Use _ra versions of cpu_stl_data() in v7M helpers
      hw/timer/armv7m_systick: Forbid non-privileged accesses
      target/arm: Execute Thumb instructions when their condbits are 0xf
      target/arm: Correct VMOV_imm_dp handling of short vectors

Philippe Mathieu-Daudé (3):
      target/arm: Move debug routines to debug_helper.c
      target/arm: Restrict semi-hosting to TCG
      target/arm/helper: Move M profile routines to m_helper.c

 target/arm/Makefile.objs       |    5 +-
 target/arm/cpu.h               |    7 +
 hw/intc/armv7m_nvic.c          |   54 +-
 hw/timer/armv7m_systick.c      |   26 +-
 target/arm/cpu.c               |    9 +-
 target/arm/debug_helper.c      |  311 +++++
 target/arm/helper.c            | 2646 +--------------------------------------
 target/arm/m_helper.c          | 2679 ++++++++++++++++++++++++++++++++++++++++
 target/arm/op_helper.c         |  295 -----
 target/arm/translate-vfp.inc.c |    2 +-
 target/arm/translate.c         |   15 +-
 11 files changed, 3096 insertions(+), 2953 deletions(-)
 create mode 100644 target/arm/debug_helper.c
 create mode 100644 target/arm/m_helper.c

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

On Thu, 4 Jul 2019 at 17:08, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> A last collection of patches to squeeze in before rc0.
> The patches from me are all bugfixes. Philippe's are just
> code-movement, but I wanted to get these into 4.1 because
> that kind of patch is so painful to have to rebase.
> (The diffstat is huge but it's just code moving from file to file.)
>
> thanks
> -- PMM
>
> The following changes since commit 234e256511e588680300600ce087c5185d68cf2a:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-build-2019-07-02-v2' into staging (2019-07-04 15:58:46 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190704
>
> for you to fetch changes up to b75f3735802b5b33f10e4bfe374d4b17bb86d29a:
>
>   target/arm: Correct VMOV_imm_dp handling of short vectors (2019-07-04 16:52:05 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * more code-movement to separate TCG-only functions into their own files
>  * Correct VMOV_imm_dp handling of short vectors
>  * Execute Thumb instructions when their condbits are 0xf
>  * armv7m_systick: Forbid non-privileged accesses
>  * Use _ra versions of cpu_stl_data() in v7M helpers
>  * v8M: Check state of exception being returned from
>  * v8M: Forcibly clear negative-priority exceptions on deactivate
>

Oops, this crossed in the post with the qapi header reorg, and
the move to m_profile.c doesn't build from clean (incremental
was fine because the old header was still lying around in the
build tree). v2 coming up shortly.

-- PMM

[Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

A last collection of patches to squeeze in before rc0.
The patches from me are all bugfixes. Philippe's are just
code-movement, but I wanted to get these into 4.1 because
that kind of patch is so painful to have to rebase.
(The diffstat is huge but it's just code moving from file to file.)

v2: fix up for clash with the qapi refactor which only
showed up in a build-from-clean.

thanks
-- PMM


The following changes since commit c3e1d838cfa5aac1a6210c8ddf182d0ef7d95dd8:

  Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190704-pull-request' into staging (2019-07-04 16:43:13 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190704-1

for you to fetch changes up to 89a11ff756410aecb87d2c774df6e45dbf4105c1:

  target/arm: Correct VMOV_imm_dp handling of short vectors (2019-07-04 17:25:30 +0100)

----------------------------------------------------------------
target-arm queue:
 * more code-movement to separate TCG-only functions into their own files
 * Correct VMOV_imm_dp handling of short vectors
 * Execute Thumb instructions when their condbits are 0xf
 * armv7m_systick: Forbid non-privileged accesses
 * Use _ra versions of cpu_stl_data() in v7M helpers
 * v8M: Check state of exception being returned from
 * v8M: Forcibly clear negative-priority exceptions on deactivate

----------------------------------------------------------------
Peter Maydell (6):
      arm v8M: Forcibly clear negative-priority exceptions on deactivate
      target/arm: v8M: Check state of exception being returned from
      target/arm: Use _ra versions of cpu_stl_data() in v7M helpers
      hw/timer/armv7m_systick: Forbid non-privileged accesses
      target/arm: Execute Thumb instructions when their condbits are 0xf
      target/arm: Correct VMOV_imm_dp handling of short vectors

Philippe Mathieu-Daudé (3):
      target/arm: Move debug routines to debug_helper.c
      target/arm: Restrict semi-hosting to TCG
      target/arm/helper: Move M profile routines to m_helper.c

 target/arm/Makefile.objs       |    5 +-
 target/arm/cpu.h               |    7 +
 hw/intc/armv7m_nvic.c          |   54 +-
 hw/timer/armv7m_systick.c      |   26 +-
 target/arm/cpu.c               |    9 +-
 target/arm/debug_helper.c      |  311 +++++
 target/arm/helper.c            | 2646 +--------------------------------------
 target/arm/m_helper.c          | 2679 ++++++++++++++++++++++++++++++++++++++++
 target/arm/op_helper.c         |  295 -----
 target/arm/translate-vfp.inc.c |    2 +-
 target/arm/translate.c         |   15 +-
 11 files changed, 3096 insertions(+), 2953 deletions(-)
 create mode 100644 target/arm/debug_helper.c
 create mode 100644 target/arm/m_helper.c

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[Peter Maydell]

On Thu, 4 Jul 2019 at 17:32, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> A last collection of patches to squeeze in before rc0.
> The patches from me are all bugfixes. Philippe's are just
> code-movement, but I wanted to get these into 4.1 because
> that kind of patch is so painful to have to rebase.
> (The diffstat is huge but it's just code moving from file to file.)
>
> v2: fix up for clash with the qapi refactor which only
> showed up in a build-from-clean.
>
> thanks
> -- PMM
>
>
> The following changes since commit c3e1d838cfa5aac1a6210c8ddf182d0ef7d95dd8:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190704-pull-request' into staging (2019-07-04 16:43:13 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190704-1
>
> for you to fetch changes up to 89a11ff756410aecb87d2c774df6e45dbf4105c1:
>
>   target/arm: Correct VMOV_imm_dp handling of short vectors (2019-07-04 17:25:30 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * more code-movement to separate TCG-only functions into their own files
>  * Correct VMOV_imm_dp handling of short vectors
>  * Execute Thumb instructions when their condbits are 0xf
>  * armv7m_systick: Forbid non-privileged accesses
>  * Use _ra versions of cpu_stl_data() in v7M helpers
>  * v8M: Check state of exception being returned from
>  * v8M: Forcibly clear negative-priority exceptions on deactivate


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

Re: [Qemu-devel] [PULL 0/9] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190704160802.12419-1-peter.maydell@linaro.org/



Hi,

This series failed build test on s390x host. Please find the details below.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e

echo
echo "=== ENV ==="
env

echo
echo "=== PACKAGES ==="
rpm -qa

echo
echo "=== UNAME ==="
uname -a

CC=$HOME/bin/cc
INSTALL=$PWD/install
BUILD=$PWD/build
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --cc=$CC --prefix=$INSTALL
make -j4
# XXX: we need reliable clean up
# make check -j4 V=1
make install
=== TEST SCRIPT END ===

  CC      lm32-softmmu/tcg/tcg-op-vec.o
  CC      lm32-softmmu/tcg/tcg-op-gvec.o
  CC      aarch64-softmmu/target/arm/m_helper.o
/var/tmp/patchew-tester-tmp-79_lp9kv/src/target/arm/m_helper.c:27:10: fatal error: qapi/qapi-commands-target.h: No such file or directory
   27 | #include "qapi/qapi-commands-target.h"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
---
  CC      arm-softmmu/target/arm/neon_helper.o
  CC      arm-softmmu/target/arm/m_helper.o
  CC      arm-softmmu/target/arm/psci.o
/var/tmp/patchew-tester-tmp-79_lp9kv/src/target/arm/m_helper.c:27:10: fatal error: qapi/qapi-commands-target.h: No such file or directory
   27 | #include "qapi/qapi-commands-target.h"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.


The full log is available at
http://patchew.org/logs/20190704160802.12419-1-peter.maydell@linaro.org/testing.s390x/?type=message.
---
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