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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 28 Oct 2016 11:46:03 -0500
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Subject: Re: [Qemu-devel] [RFC] powernv: CPU compatibility modes don't make
 sense for powernv
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To: =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>, David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On Fri, 2016-10-28 at 18:40 +0200, C=C3=A9dric Le Goater wrote:
>=C2=A0
> It makes perfect sense. The "cpu-version" property is for PAPR, not
> for OPAL.
> hostboot and skiboot put SPR_PVR in this property.=C2=A0
>=20
> I will be careful using 'CPU_CORE(pc)->nr_threads' in the ICP patches
> also.=C2=A0

No, the cpu-version is part of the old OF bindings afaik, at least it
exists under OPAL, so it should be there but yes, it should just
contain the PVR.

Cheers,
Ben.

> Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>
>=20
> Thanks,
>=20
> C.
>=20
>=20
> >=20
> >=20
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 82276e0..6af3424 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -110,7 +110,7 @@ static void powernv_create_core_node(PnvChip
> > *chip, PnvCore *pc, void *fdt)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUState *cs =3D CPU(DEVICE(pc->threads=
));
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0DeviceClass *dc =3D DEVICE_GET_CLASS(cs=
);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0PowerPCCPU *cpu =3D POWERPC_CPU(cs);
> > -=C2=A0=C2=A0=C2=A0=C2=A0int smt_threads =3D ppc_get_compat_smt_threa=
ds(cpu);
> > +=C2=A0=C2=A0=C2=A0=C2=A0int smt_threads =3D CPU_CORE(pc)->nr_threads=
;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUPPCState *env =3D &cpu->env;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0PowerPCCPUClass *pcc =3D POWERPC_CPU_GE=
T_CLASS(cs);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint32_t servers_prop[smt_threads];
> > @@ -206,10 +206,6 @@ static void powernv_create_core_node(PnvChip
> > *chip, PnvCore *pc, void *fdt)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0_FDT((fdt_setprop(fdt, offset, "ibm,pa-=
features",
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
pa_features, sizeof(pa_features))));
> > =C2=A0
> > -=C2=A0=C2=A0=C2=A0=C2=A0if (cpu->cpu_version) {
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0_FDT((fdt_setprop_ce=
ll(fdt, offset, "cpu-version", cpu-
> > >cpu_version)));
> > -=C2=A0=C2=A0=C2=A0=C2=A0}
> > -
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* Build interrupt servers properties *=
/
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0for (i =3D 0; i < smt_threads; i++) {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0servers_prop[i]=
 =3D cpu_to_be32(pc->pir + i);
> >=20