From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c0BEh-0000Gp-LH for qemu-devel@nongnu.org; Fri, 28 Oct 2016 13:46:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c0BEd-0006hi-QE for qemu-devel@nongnu.org; Fri, 28 Oct 2016 13:46:35 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:48550 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c0BEd-0006hX-JK for qemu-devel@nongnu.org; Fri, 28 Oct 2016 13:46:31 -0400 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u9SHhrYe141409 for ; Fri, 28 Oct 2016 13:46:30 -0400 Received: from e24smtp04.br.ibm.com (e24smtp04.br.ibm.com [32.104.18.25]) by mx0b-001b2d01.pphosted.com with ESMTP id 26c91du7w2-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 28 Oct 2016 13:46:30 -0400 Received: from localhost by e24smtp04.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 28 Oct 2016 15:46:28 -0200 Received: from d24relay03.br.ibm.com (d24relay03.br.ibm.com [9.18.232.225]) by d24dlp02.br.ibm.com (Postfix) with ESMTP id B38201DC0088 for ; Fri, 28 Oct 2016 13:46:26 -0400 (EDT) Received: from d24av01.br.ibm.com (d24av01.br.ibm.com [9.8.31.91]) by d24relay03.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u9SHkQnk35192922 for ; Fri, 28 Oct 2016 15:46:26 -0200 Received: from d24av01.br.ibm.com (localhost [127.0.0.1]) by d24av01.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u9SHkQep009777 for ; Fri, 28 Oct 2016 15:46:26 -0200 From: Jose Ricardo Ziviani Date: Fri, 28 Oct 2016 15:46:19 -0200 Message-Id: <1477676782-21378-1-git-send-email-joserz@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH Risu 0/3] Risu support for PPC64LE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org From: Jose Ricardo Ziviani This is an initial effort to have RISU working for PPC64LE. I also made some changes to isolate risugen, creating two modules (risugen_arm.pm and risugen_ppc64le.pm) to implement specific instructions in it. Suggestions are welcome! :) TODOS: - improve load/store instruction generation - improve initial random values for FP and Vector regs. Jose Ricardo Ziviani (3): Implementation of ppc64le module for risugen and risufile Isolates Arm specific subroutines out from risugen main file Initial implemention for ppc64le configure | 6 + ppc64le.risu | 3459 ++++++++++++++++++++++++++++++++++++++++++++++++ risu_ppc64le.c | 92 ++ risu_reginfo_ppc64le.c | 175 +++ risu_reginfo_ppc64le.h | 36 + risugen | 1018 +------------- risugen_arm.pm | 1075 +++++++++++++++ risugen_ppc64le.pm | 460 +++++++ test_ppc64le.s | 52 + 9 files changed, 5385 insertions(+), 988 deletions(-) create mode 100644 ppc64le.risu create mode 100644 risu_ppc64le.c create mode 100644 risu_reginfo_ppc64le.c create mode 100644 risu_reginfo_ppc64le.h create mode 100644 risugen_arm.pm create mode 100644 risugen_ppc64le.pm create mode 100644 test_ppc64le.s -- 2.7.4