* [Qemu-devel] [PATCH v2 1/2] target-m68k: add 64bit mull
2016-10-28 23:01 [Qemu-devel] [PATCH v2 0/2] 680x0 mul and div instructions Laurent Vivier
@ 2016-10-28 23:01 ` Laurent Vivier
2016-10-31 12:48 ` Richard Henderson
2016-10-28 23:01 ` [Qemu-devel] [PATCH v2 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
1 sibling, 1 reply; 6+ messages in thread
From: Laurent Vivier @ 2016-10-28 23:01 UTC (permalink / raw)
To: qemu-devel; +Cc: schwab, agraf, Richard Henderson, gerg, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/translate.c | 60 +++++++++++++++++++++++++++++++++++++++----------
1 file changed, 48 insertions(+), 12 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index c00978d..d612a82 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1812,24 +1812,60 @@ DISAS_INSN(tas)
DISAS_INSN(mull)
{
uint16_t ext;
- TCGv reg;
TCGv src1;
- TCGv dest;
+ int sign;
- /* The upper 32 bits of the product are discarded, so
- muls.l and mulu.l are functionally equivalent. */
ext = read_im16(env, s);
- if (ext & 0x87ff) {
- gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+
+ sign = ext & 0x800;
+
+ if (ext & 0x400) {
+ if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
+ gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+ return;
+ }
+
+ SRC_EA(env, src1, OS_LONG, 0, NULL);
+
+ if (sign) {
+ tcg_gen_muls2_i32(DREG(ext, 12), DREG(ext, 0), src1, DREG(ext, 12));
+ } else {
+ tcg_gen_mulu2_i32(DREG(ext, 12), DREG(ext, 0), src1, DREG(ext, 12));
+ }
+
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_V);
+ tcg_gen_mov_i32(QREG_CC_N, DREG(ext, 0));
+ tcg_gen_or_i32(QREG_CC_Z, DREG(ext, 12), DREG(ext, 0));
+
+ set_cc_op(s, CC_OP_FLAGS);
return;
}
- reg = DREG(ext, 12);
SRC_EA(env, src1, OS_LONG, 0, NULL);
- dest = tcg_temp_new();
- tcg_gen_mul_i32(dest, src1, reg);
- tcg_gen_mov_i32(reg, dest);
- /* Unlike m68k, coldfire always clears the overflow bit. */
- gen_logic_cc(s, dest, OS_LONG);
+ if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+ if (sign) {
+ tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
+ /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
+ tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
+ } else {
+ tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
+ /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
+ }
+ tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
+ tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
+
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+
+ set_cc_op(s, CC_OP_FLAGS);
+ } else {
+ /* The upper 32 bits of the product are discarded, so
+ muls.l and mulu.l are functionally equivalent. */
+ tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
+ gen_logic_cc(s, DREG(ext, 12), OS_LONG);
+ }
}
static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH v2 2/2] target-m68k: add 680x0 divu/divs variants
2016-10-28 23:01 [Qemu-devel] [PATCH v2 0/2] 680x0 mul and div instructions Laurent Vivier
2016-10-28 23:01 ` [Qemu-devel] [PATCH v2 1/2] target-m68k: add 64bit mull Laurent Vivier
@ 2016-10-28 23:01 ` Laurent Vivier
2016-10-31 13:06 ` Richard Henderson
1 sibling, 1 reply; 6+ messages in thread
From: Laurent Vivier @ 2016-10-28 23:01 UTC (permalink / raw)
To: qemu-devel; +Cc: schwab, agraf, Richard Henderson, gerg, Laurent Vivier
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
linux-user/main.c | 7 +++
target-m68k/cpu.h | 4 --
target-m68k/helper.h | 6 +-
target-m68k/op_helper.c | 102 ++++++++++++++++++++++++--------
target-m68k/qregs.def | 2 -
target-m68k/translate.c | 154 ++++++++++++++++++++++++++++++++++++++----------
6 files changed, 211 insertions(+), 64 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 75b199f..c1d5eb4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2864,6 +2864,13 @@ void cpu_loop(CPUM68KState *env)
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_DIV0:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = TARGET_FPE_INTDIV;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_TRAP0:
{
abi_long ret;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 6dfb54e..0b4ed7b 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -95,10 +95,6 @@ typedef struct CPUM68KState {
uint32_t macsr;
uint32_t mac_mask;
- /* Temporary storage for DIV helpers. */
- uint32_t div1;
- uint32_t div2;
-
/* MMU status. */
struct {
uint32_t ar;
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index aae01f9..566094a 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -1,8 +1,10 @@
DEF_HELPER_1(bitrev, i32, i32)
DEF_HELPER_1(ff1, i32, i32)
DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-DEF_HELPER_2(divu, void, env, i32)
-DEF_HELPER_2(divs, void, env, i32)
+DEF_HELPER_4(divu, i64, env, i32, i32, i32)
+DEF_HELPER_4(divs, i64, env, i32, i32, i32)
+DEF_HELPER_3(divu64, i64, env, i64, i32)
+DEF_HELPER_3(divs64, i64, env, i64, i32)
DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 48e02e4..cdeeb10 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -166,12 +166,17 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
-static void raise_exception(CPUM68KState *env, int tt)
+static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
CPUState *cs = CPU(m68k_env_get_cpu(env));
cs->exception_index = tt;
- cpu_loop_exit(cs);
+ cpu_loop_exit_restore(cs, raddr);
+}
+
+static void raise_exception(CPUM68KState *env, int tt)
+{
+ raise_exception_ra(env, tt, 0);
}
void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
@@ -179,51 +184,100 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
raise_exception(env, tt);
}
-void HELPER(divu)(CPUM68KState *env, uint32_t word)
+uint64_t HELPER(divu)(CPUM68KState *env, uint32_t num, uint32_t den,
+ uint32_t word)
{
- uint32_t num;
- uint32_t den;
uint32_t quot;
uint32_t rem;
- num = env->div1;
- den = env->div2;
- /* ??? This needs to make sure the throwing location is accurate. */
if (den == 0) {
- raise_exception(env, EXCP_DIV0);
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
}
quot = num / den;
rem = num % den;
env->cc_v = (word && quot > 0xffff ? -1 : 0);
- env->cc_z = quot;
- env->cc_n = quot;
+ /* real 68040 keep Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ if (!env->cc_v) {
+ env->cc_z = quot;
+ env->cc_n = quot;
+ }
env->cc_c = 0;
- env->div1 = quot;
- env->div2 = rem;
+ return quot | ((uint64_t)rem << 32);
}
-void HELPER(divs)(CPUM68KState *env, uint32_t word)
+uint64_t HELPER(divs)(CPUM68KState *env, uint32_t num, uint32_t den,
+ uint32_t word)
{
- int32_t num;
- int32_t den;
int32_t quot;
int32_t rem;
- num = env->div1;
- den = env->div2;
if (den == 0) {
- raise_exception(env, EXCP_DIV0);
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = (int32_t)num / (int32_t)den;
+ rem = (int32_t)num % (int32_t)den;
+
+ env->cc_v = (word && quot != (int16_t)quot ? -1 : 0);
+ /* real 68040 keep Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ if (!env->cc_v) {
+ env->cc_z = quot;
+ env->cc_n = quot;
+ }
+ env->cc_c = 0;
+
+ return quot | ((uint64_t)rem << 32);
+}
+
+uint64_t HELPER(divu64)(CPUM68KState *env, uint64_t num, uint32_t den)
+{
+ uint64_t quot;
+ uint32_t rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
}
quot = num / den;
rem = num % den;
- env->cc_v = (word && quot != (int16_t)quot ? -1 : 0);
- env->cc_z = quot;
- env->cc_n = quot;
+ env->cc_v = quot > 0xffffffffULL ? -1 : 0;
+ /* real 68040 keep Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ if (!env->cc_v) {
+ env->cc_z = quot;
+ env->cc_n = quot;
+ }
+ env->cc_c = 0;
+
+ return quot | ((uint64_t)rem << 32);
+}
+
+uint64_t HELPER(divs64)(CPUM68KState *env, uint64_t num, uint32_t den)
+{
+ int64_t quot;
+ int32_t rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = num / (int64_t)den;
+ rem = num % (int64_t)den;
+
+ env->cc_v = !((quot >> 31) == 0 || (quot >> 31) == -1) ? -1 : 0;
+ /* real 68040 keep Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ if (!env->cc_v) {
+ env->cc_z = quot;
+ env->cc_n = quot;
+ }
env->cc_c = 0;
- env->div1 = quot;
- env->div2 = rem;
+ return quot | ((uint64_t)rem << 32);
}
diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def
index 156c0f5..51ff43b 100644
--- a/target-m68k/qregs.def
+++ b/target-m68k/qregs.def
@@ -7,7 +7,5 @@ DEFO32(CC_C, cc_c)
DEFO32(CC_N, cc_n)
DEFO32(CC_V, cc_v)
DEFO32(CC_Z, cc_z)
-DEFO32(DIV1, div1)
-DEFO32(DIV2, div2)
DEFO32(MACSR, macsr)
DEFO32(MAC_MASK, mac_mask)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d612a82..e011304 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1191,64 +1191,154 @@ DISAS_INSN(mulw)
DISAS_INSN(divw)
{
- TCGv reg;
- TCGv tmp;
TCGv src;
int sign;
+ TCGv word;
+ TCGv_i64 t64;
+ TCGv_i32 quot, rem;
+
+ /* divX.w <EA>,Dn 32/16 -> 16r:16q */
sign = (insn & 0x100) != 0;
- reg = DREG(insn, 9);
+
+ /* dest.l / src.w */
+
+ SRC_EA(env, src, OS_WORD, sign, NULL);
+
+ t64 = tcg_temp_new_i64();
+ word = tcg_const_i32(1);
if (sign) {
- tcg_gen_ext16s_i32(QREG_DIV1, reg);
+ gen_helper_divs(t64, cpu_env, DREG(insn, 9), src, word);
} else {
- tcg_gen_ext16u_i32(QREG_DIV1, reg);
+ gen_helper_divu(t64, cpu_env, DREG(insn, 9), src, word);
}
- SRC_EA(env, src, OS_WORD, sign, NULL);
- tcg_gen_mov_i32(QREG_DIV2, src);
+ tcg_temp_free(word);
+
+ /* result rem.w:quot.w */
+
+ quot = tcg_temp_new_i32();
+ rem = tcg_temp_new_i32();
+ tcg_gen_extr_i64_i32(quot, rem, t64);
+ tcg_temp_free_i64(t64);
+ tcg_gen_deposit_i32(quot, quot, rem, 16, 16);
+ tcg_temp_free_i32(rem);
+
+ /* on overflow, operands are unaffected,
+ * Z and N flags are undefined, C is always 0
+ */
+
+ tcg_gen_movcond_i32(TCG_COND_EQ, DREG(insn, 9),
+ QREG_CC_V, QREG_CC_C /* zero */,
+ quot, DREG(insn, 9));
+ tcg_temp_free_i32(quot);
+
+ set_cc_op(s, CC_OP_FLAGS);
+}
+
+static void do_div64(int sign, TCGv num, TCGv reg, TCGv den)
+{
+ TCGv_i64 t64;
+ TCGv_i32 quot, rem;
+
+ t64 = tcg_temp_new_i64();
+ tcg_gen_concat_i32_i64(t64, num, reg);
+
if (sign) {
- gen_helper_divs(cpu_env, tcg_const_i32(1));
+ gen_helper_divs64(t64, cpu_env, t64, den);
} else {
- gen_helper_divu(cpu_env, tcg_const_i32(1));
+ gen_helper_divu64(t64, cpu_env, t64, den);
}
- tmp = tcg_temp_new();
- src = tcg_temp_new();
- tcg_gen_ext16u_i32(tmp, QREG_DIV1);
- tcg_gen_shli_i32(src, QREG_DIV2, 16);
- tcg_gen_or_i32(reg, tmp, src);
+ quot = tcg_temp_new_i32();
+ rem = tcg_temp_new_i32();
+ tcg_gen_extr_i64_i32(quot, rem, t64);
+ tcg_temp_free_i64(t64);
- set_cc_op(s, CC_OP_FLAGS);
+ /* on overflow, operands are unaffected,
+ * Z and N flags are undefined, C is always 0
+ * If Dq and Dr are the same, the quotient is returned.
+ * therefore we set Dq last.
+ */
+
+ tcg_gen_movcond_i32(TCG_COND_EQ, reg,
+ QREG_CC_V, QREG_CC_C /* zero */ ,
+ rem, reg);
+ tcg_temp_free_i32(rem);
+ tcg_gen_movcond_i32(TCG_COND_EQ, num,
+ QREG_CC_V, QREG_CC_C /* zero */ ,
+ quot, num);
+ tcg_temp_free_i32(quot);
}
DISAS_INSN(divl)
{
- TCGv num;
TCGv den;
- TCGv reg;
+ TCGv word;
+ int sign;
uint16_t ext;
+ TCGv_i64 t64;
+ TCGv_i32 quot, rem;
ext = read_im16(env, s);
- if (ext & 0x87f8) {
- gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+
+ sign = (ext & 0x0800) != 0;
+
+ if (ext & 0x400) {
+ if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
+ gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ return;
+ }
+ /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
+ SRC_EA(env, den, OS_LONG, 0, NULL);
+ do_div64(sign, DREG(ext, 12), DREG(ext, 0), den);
+ set_cc_op(s, CC_OP_FLAGS);
return;
}
- num = DREG(ext, 12);
- reg = DREG(ext, 0);
- tcg_gen_mov_i32(QREG_DIV1, num);
SRC_EA(env, den, OS_LONG, 0, NULL);
- tcg_gen_mov_i32(QREG_DIV2, den);
- if (ext & 0x0800) {
- gen_helper_divs(cpu_env, tcg_const_i32(0));
+
+ t64 = tcg_temp_new_i64();
+ word = tcg_const_i32(0);
+ if (sign) {
+ gen_helper_divs(t64, cpu_env, DREG(ext, 12), den, word);
} else {
- gen_helper_divu(cpu_env, tcg_const_i32(0));
+ gen_helper_divu(t64, cpu_env, DREG(ext, 12), den, word);
}
- if ((ext & 7) == ((ext >> 12) & 7)) {
- /* div */
- tcg_gen_mov_i32 (reg, QREG_DIV1);
+ tcg_temp_free(word);
+
+ quot = tcg_temp_new_i32();
+ rem = tcg_temp_new_i32();
+ tcg_gen_extr_i64_i32(quot, rem, t64);
+ tcg_temp_free_i64(t64);
+
+ /* on overflow, operands are unaffected,
+ * Z and N flags are undefined, C is always 0
+ * If Dq and Dr are the same, the quotient is returned.
+ * therefore we set Dq last.
+ */
+ if (m68k_feature(s->env, M68K_FEATURE_CF_ISA_A)) {
+ /* divs.l <EA>, Dq 32/32 -> 32q */
+ if (REG(ext, 0) == REG(ext, 12)) {
+ tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 12),
+ QREG_CC_V, QREG_CC_C /* zero */,
+ quot, DREG(ext, 12)); /* quot */
+ } else {
+ tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 0),
+ QREG_CC_V, QREG_CC_C /* zero */,
+ rem, DREG(ext, 0)); /* rem */
+ }
} else {
- /* rem */
- tcg_gen_mov_i32 (reg, QREG_DIV2);
- }
+ /* divs.l <EA>, Dq 32/32 -> 32q */
+ /* divsl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
+ tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 0),
+ QREG_CC_V, QREG_CC_C /* zero */,
+ rem, DREG(ext, 0)); /* rem */
+ tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 12),
+ QREG_CC_V, QREG_CC_C /* zero */,
+ quot, DREG(ext, 12)); /* quot */
+ }
+ tcg_temp_free_i32(rem);
+ tcg_temp_free_i32(quot);
+
set_cc_op(s, CC_OP_FLAGS);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread